Techniques to communicate with a controller for a non-volatile dual in-line memory module
First Claim
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1. An apparatus comprising:
- circuitry at a controller for a non-volatile memory capable of preserving data maintained in volatile memory, the non-volatile and the volatile memory resident on a non-volatile dual in-line memory module (NVDIMM), the NVDIMM comprising a first set of registers, a second set of registers, and a third set of registers;
a receive component for execution by the circuitry to receive a status request and a first command, the first command to be received via assertion of a first set of bits maintained in the first set of registers, the assertion of the first set of bits based on a register map;
a status component for execution by the circuitry to determine a status responsive to the status request; and
an indicate component for execution by the circuitry to indicate the status via selective assertion of a second set of bits maintained in the second set of registers and to indicate acceptance and completion status of the first command via assertion of a third set of bits maintained in a third set of registers of the NVDIMM, the selective assertion based on the register map and the assertion of the third set of bits based on the register map.
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Abstract
Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.
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Citations
25 Claims
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1. An apparatus comprising:
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circuitry at a controller for a non-volatile memory capable of preserving data maintained in volatile memory, the non-volatile and the volatile memory resident on a non-volatile dual in-line memory module (NVDIMM), the NVDIMM comprising a first set of registers, a second set of registers, and a third set of registers; a receive component for execution by the circuitry to receive a status request and a first command, the first command to be received via assertion of a first set of bits maintained in the first set of registers, the assertion of the first set of bits based on a register map; a status component for execution by the circuitry to determine a status responsive to the status request; and an indicate component for execution by the circuitry to indicate the status via selective assertion of a second set of bits maintained in the second set of registers and to indicate acceptance and completion status of the first command via assertion of a third set of bits maintained in a third set of registers of the NVDIMM, the selective assertion based on the register map and the assertion of the third set of bits based on the register map. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method comprising:
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receiving, at a controller, a status request, the controller for a non-volatile memory capable of preserving data maintained in volatile memory, the non-volatile and the volatile memory resident on a non-volatile dual in-line memory module (NVDIMM); determining a status responsive to the status request; indicating the status via selective assertion of a first set of bits maintained in a first set of registers of the NVDIMM, the selective assertion based on a register map; receiving, at the controller, a first command via assertion of a second set of bits maintained in a second set of registers of the NVDIMM, the assertion of the second set of bits based on the register map; and indicating acceptance and completion status of the first command via assertion of a third set of bits maintained in a third set of registers of the NVDIMM, the assertion of the third set of bits based on the register map. - View Dependent Claims (15, 16, 17, 18, 19)
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20. At least one non-transitory machine readable medium comprising a plurality of instructions that in response to being executed by system at a host computing platform cause the system to:
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send a status request to a controller for a non-volatile memory capable of preserving data maintained in volatile memory, the non-volatile and the volatile memory resident on a non-volatile dual in-line memory module (NVDIMM) coupled with the host computing platform; access a first set of bits maintained in a first set of registers of the NVDIMM through a system management bus (SMBus) interface, the first set of bits indicating a status indicated by the controller responsive to the status request via selective asserting of the first set of bits based on a register map; send a command via assertion of a second set of bits maintained in a second set of registers of the NVDIMM, the assertion of the second set of bits based on the register map; and receive an indication of acceptance and completion status of the command via a third set of bits maintained in a third set of registers of the NVDIMM. - View Dependent Claims (21, 22)
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23. A system comprising:
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circuitry for a host computing platform to implement a basic input/output system (BIOS), an application or a device driver; a non-volatile dual in-line memory module (NVDIMM) having resident non-volatile memory and volatile memory, the non-volatile memory capable of preserving data maintained in a volatile memory; and a controller for the non-volatile memory, the controller operative to; receive a status request from the BIOS, the application or the device driver, the status request comprising a request for a health status of the NVDIMM, a state of the controller or a state of the NVDIMM; determine a status responsive to the status request; indicate the status via selective assertion of a first set of bits maintained in a first set of registers of the NVDIMM, the selective assertion based on a register map; and receive a command from the BIOS, the application or the device driver via assertion of a second set of bits maintained in a second set of registers of the NVDIMM, the assertion of the second set of bits based on the register map. - View Dependent Claims (24, 25)
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Specification