Data storage device and flash memory control method

• US 9,645,894 B2
• Filed: 11/06/2014
• Issued: 05/09/2017
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Lin, Chien-Cheng, Liang, Chia-Chi, Huang, Chang-Chieh, Lee, Jie-Hao
• Primary Examiner(s): Riad, Amine
• Application Number:
  US14/534,535
• Publication Number:
  US 20150186224A1
• Time in Patent Office: 915 Days
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2029/0411 : Online error correction
• CPC Class Codes: G11C 2211/5641 : Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage device and a flash memory control method with a power recovery design. A microcontroller is configured to allocate a flash memory to provide a first block from the blocks to work as a run-time write block for reception of write data. During a power recovery process due to an unexpected power-off event that interrupted write operations on the first block, the microcontroller is configured to allocate the flash memory to provide a second block from the blocks for complete data recovery of the first block and to replace the first block as the run-time write block.

Claims

1. A data storage device, comprising:

a flash memory, divided into a plurality of blocks with each block comprising a plurality of pages; and

a control unit, coupling the flash memory to a host and comprising a microcontroller,

wherein the microcontroller is configured to allocate the flash memory to provide a first block from the blocks to work as a run-time write block for reception of write data and, during a power recovery process due to an unexpected power-off event that interrupted write operations on the first block, the microcontroller is configured to allocate the flash memory to provide a second block from the blocks for complete data recovery of the first block and to replace the first block as the run-time write block, wherein the microcontroller is configured to allocate the flash memory to provide the first block as the run-time write block when finishing writing of a table-outdated block between the blocks of the flash memory, the control unit further comprises a random access memory, the microcontroller is configured to establish a physical-to-logical address mapping table in the random access memory to record logical addresses corresponding to physical addresses of the table-outdated block, and the microcontroller is configured to update a logical-to-physical address mapping table in accordance with the physical-to-logical address mapping table at intervals longer than a time-out period between write operations on the run-time write block.

2. The data storage device as claimed in claim 1, wherein:

the microcontroller is configured to allocate the flash memory to provide the first block as the run-time write block when the table-outdated block is full;

and

the logical-to-physical address mapping table is provided within the flash memory.

3. The data storage device as claimed in claim 2, wherein:

between a first write operation and a second write operation on the run-time write block, the microcontroller updates the logical-to-physical address mapping table in accordance with just part of the physical-to-logical address mapping table.

4. The data storage device as claimed in claim 2, wherein:

during the power recovery process due to the unexpected power-off event that interrupted write operations on the first block, the microcontroller restores the physical-to-logical mapping table based on physical-to-logical mapping information stored in the table-outdated block.

5. The data storage device as claimed in claim 1, wherein:

during a power recovery process due to an unexpected power-off event that interrupted write operations on the second block, the microcontroller is configured to invalidate the second block and allocate the flash memory to provide a third block from the blocks for complete data recovery of the first block and to replace the first block as the run-time write block.

6. The data storage device as claimed in claim 1, wherein:

the microcontroller is configured to perform the complete data recovery of the first block based on an error checking and correction algorithm.

7. A flash memory control method, comprising:

allocating a flash memory to provide a first block from a plurality of blocks of the flash memory to work as a run-time write block for reception of write data;

during a power recovery process due to an unexpected power-off event that interrupted write operations on the first block, allocating the flash memory to provide a second block from the blocks for complete data recovery of the first block and to replace the first block as the run-time write block;

allocating the flash memory to provide the first block as the run-time write block when finishing writing of a table-outdated block between the blocks of the flash memory;

establishing a physical-to-logical address mapping table in a random access memory to record logical addresses corresponding to physical addresses of the table-outdated block; and

updating a logical-to-physical address mapping table in accordance with the physical-to-logical address mapping table at intervals longer than a time-out period between write operations on the run-time write block.

8. The flash memory control method as claimed in claim 7, further comprising:

allocating the flash memory to provide the first block as the run-time write block during a power recovery process due to an unexpected power-off event that interrupted write operations on the table-outdated block;

wherein the logical-to-physical address mapping table is provided within the flash memory.

9. The flash memory control method as claimed in claim 8, wherein:

between a first write operation and a second write operation on the run-time write block, the logical-to-physical address mapping table is updated in accordance with just part of the physical-to-logical address mapping table.

10. The flash memory control method as claimed in claim 8, wherein:

during the power recovery process due to the unexpected power-off event that interrupted write operations on the first block, the physical-to-logical mapping table is restored based on physical-to-logical mapping information stored in the table-outdated block.

11. The flash memory control method as claimed in claim 7, further comprising:

during a power recovery process due to an unexpected power-off event that interrupted write operations on the second block, invaliding the second block and allocating the flash memory to provide a third block from the blocks for complete data recovery of the first block and to replace the first block as the run-time write block.

12. The flash memory control method as claimed in claim 7, wherein:

the complete data recovery of the first block is performed based on an error checking and correction algorithm.