Data storage device and flash memory control method

• US 9,645,895 B2
• Filed: 11/06/2014
• Issued: 05/09/2017
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Lin, Chien-Cheng, Liang, Chia-Chi, Huang, Chang-Chieh, Lee, Jie-Hao
• Primary Examiner(s): Perez-Velez, Rocio Del Mar
• Application Number:
  US14/534,569
• Publication Number:
  US 20150186225A1
• Time in Patent Office: 915 Days
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2029/0411 : Online error correction
• CPC Class Codes: G11C 2211/5641 : Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to establish a first physical-to-logical address mapping table (F2H table) in a random access memory (RAM) for a first run-time write block containing MLCs. The microcontroller is further configured to establish a second F2H table in the RAM for a second run-time write block containing SLCs. When data that was previously stored in the first run-time write block with un-uploaded mapping information in the first F2H table is updated into the second run-time write block, the microcontroller is configured to update a logical-to-physical address mapping table (H2F table) in accordance with the first F2H table. The H2F table is provided within the flash memory.

Claims

1. A data storage device, comprising:

a flash memory including multi-level cells and single-level cells, wherein the flash memory is divided into a plurality of blocks with each block comprising a plurality of pages; and

a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,

wherein;

the microcontroller is configured to establish a first physical-to-logical address mapping table in the random access memory for a first run-time write block between the blocks of the flash memory, and the first run-time write block contains multi-level cells;

the microcontroller is further configured to establish a second physical-to-logical address mapping table in the random access memory for a second run-time write block between the blocks of the flash memory, and the second run-time write block contains single-level cells;

in response to data that was previously stored in the first run-time write block with mapping information in the first physical-to-logical address mapping table, but not yet uploaded to the flash memory, being updated into the second run-time write block, the microcontroller is configured to update a logical-to-physical address mapping table located in the flash memory in accordance with the first physical-to-logical address mapping table.

2. The data storage device as claimed in claim 1, wherein:

the microcontroller is configured to check the first physical-to-logical address mapping table to determine whether data written into to the second run-time write block was previously stored in the first run-time write block with mapping information, not yet uploaded to the flash memory, in the first physical-to-logical address mapping table.

3. The data storage device as claimed in claim 1, wherein:

after determining that the data written into to the second run-time write block was previously stored in the first run-time write block with mapping information, not yet uploaded to the flash memory, in the first physical-to-logical address mapping table, and after updating the logical-to-physical address mapping table in accordance with the first physical-to-logical address mapping table, the microcontroller continues using the first run-time write block.

4. The data storage device as claimed in claim 1, wherein:

the microcontroller is configured to allocate the flash memory to provide the first run-time write block when a first table-outdated block between the blocks of the flash memory and containing multi-level cells and corresponding to a third physical-to-logical address mapping table is full, the third physical-to-logical address mapping table is established in the random access memory; and

the microcontroller is configured to update the logical-to-physical address mapping table in accordance with the third physical-to-logical address mapping table in intervals between write operations of the first run-time write block.

5. The data storage device as claimed in claim 4, wherein:

the microcontroller is configured to allocate the flash memory to provide the second run-time write block when a second table-outdated block between the blocks of the flash memory and containing single-level cells and corresponding to a fourth physical-to-logical address mapping table is full, the fourth physical-to-logical address mapping table is established in the random access memory; and

the microcontroller is configured to update the logical-to-physical address mapping table in accordance with the fourth physical-to-logical address mapping table in intervals between write operations of the second run-time write block.

6. The data storage device as claimed in claim 1, wherein:

the microcontroller is configured to allocate the flash memory to provide the first run-time write block in a power recovery process when a write operation on a first table-outdated block between the blocks of the flash memory and containing multi-level cells and corresponding to a third physical-to-logical address mapping table was interrupted by an unexpected power-off event, the third physical-to-logical address mapping table is established in the random access memory; and

the microcontroller is configured to restore the third physical-to-logical address mapping table in the power recovery process and update the logical-to-physical address mapping table in accordance with the restored third physical-to-logical address mapping table in intervals between write operations of the first run-time-write block.

7. The data storage device as claimed in claim 6, wherein:

the microcontroller is configured to allocate the flash memory to provide the second run-time write block in the power recovery process when a write operation on a second table-outdated block between the blocks of the flash memory and containing single-level cells and corresponding to a fourth physical-to-logical address mapping table was interrupted by an unexpected power-off event, the fourth physical-to-logical address mapping table is established in the random access memory; and

the microcontroller is configured to restore the fourth physical-to-logical address mapping table in the power recovery process and update the logical-to-physical address mapping table in accordance with the restored fourth physical-to-logical address mapping table in intervals between write operations of the second run-time-write block.

8. The data storage device as claimed in claim 3, wherein:

after determining that the data written into to the second run-time write block was previously stored in the first run-time write block with mapping information, not yet uploaded to the flash memory, in the first physical-to-logical address mapping table, and after updating the logical-to-physical address mapping table in accordance with the first physical-to-logical address mapping table, the microcontroller continues using the first run-time write block only a spare area therein which does not include pages paired with those whose mapping information has been uploaded onto the logical-to-physical address mapping table.

9. A flash memory control method, comprising:

establishing a first physical-to-logical address mapping table in a random access memory for a first run-time write block between a plurality of blocks of a flash memory, each block of the flash memory comprising a plurality of pages and the first run-time write block containing multi-level cells;

establishing a second physical-to-logical address mapping table in the random access memory for a second run-time write block between the blocks of the flash memory, the second run-time write block containing single-level cells; and

updating a logical-to-physical address mapping table located in the flash memory in accordance with the first physical-to-logical address mapping table in response to data that was previously stored in the first run-time write block with mapping information not yet uploaded to the flash memory, in the first physical-to-logical address mapping table being updated into the second run-time write block.

10. The flash memory control method as claimed in claim 9, further comprising:

checking the first physical-to-logical address mapping table to determine whether data written into to the second run-time write block was previously stored in the first run-time write block with mapping information, not yet uploaded to the flash memory, in the first physical-to-logical address mapping table.

11. The flash memory control method as claimed in claim 9, further comprising:

continuing using the first run-time write block after determining that the data written into to the second run-time write block was previously stored in the first run-time write block with mapping information, not yet uploaded to the flash memory, in the first physical-to-logical address mapping table and after updating the logical-to-physical address mapping table in accordance with the first physical-to-logical address mapping table.

12. The flash memory control method as claimed in claim 9, further comprising:

allocating the flash memory to provide the first run-time write block when a first table-outdated block between the blocks of the flash memory and containing multi-level cells and corresponding to a third physical-to-logical address mapping table is full, the third physical-to-logical address mapping table is established in the random access memory; and

updating the logical-to-physical address mapping table in accordance with the third physical-to-logical address mapping table in intervals between write operations of the first run-time write block.

13. The flash memory control method as claimed in claim 12, further comprising:

allocating the flash memory to provide the second run-time write block when a second table-outdated block between the blocks of the flash memory and containing single-level cells and corresponding to a fourth physical-to-logical address mapping table is full, the fourth physical-to-logical address mapping table is established in the random access memory; and

updating the logical-to-physical address mapping table in accordance with the fourth physical-to-logical address mapping table in intervals between write operations of the second run-time write block.

14. The flash memory control method as claimed in claim 9, further comprising:

allocating the flash memory to provide the first run-time write block in a power recovery process when a write operation on a first table-outdated block between the blocks of the flash memory and containing multi-level cells and corresponding to a third physical-to-logical address mapping table was interrupted by an unexpected power-off event, the third physical-to-logical address mapping table is established in the random access memory; and

restoring the third physical-to-logical address mapping table in the power recovery process and updating the logical-to-physical address mapping table in accordance with the restored third physical-to-logical address mapping table in intervals between write operations of the first run-time-write block.

15. The flash memory control method as claimed in claim 14, further comprising:

allocating the flash memory to provide the second run-time write block in the power recovery process when a write operation on a second table-outdated block between the blocks of the flash memory and containing single-level cells and corresponding to a fourth physical-to-logical address mapping table was interrupted by an unexpected power-off event, the fourth physical-to-logical address mapping table is established in the random access memory; and

restoring the fourth physical-to-logical address mapping table in the power recovery process and updating the logical-to-physical address mapping table in accordance with the restored fourth physical-to-logical address mapping table in intervals between write operations of the second run-time-write block.

16. The flash memory control method as claimed in claim 9, further comprising:

after determining that the data written into to the second run-time write block was previously stored in the first run-time write block with mapping information, not yet uploaded to the flash memory, in the first physical-to-logical address mapping table, and after updating the logical-to-physical address mapping table in accordance with the first physical-to-logical address mapping table, continuing using the first run-time write block only a spare area therein which does not include pages paired with those whose mapping information has been uploaded onto the logical-to-physical address mapping table.