Managing wake-on-voice buffer quality based on system boot profiling

• US 9,646,607 B2
• Filed: 03/10/2014
• Issued: 05/09/2017
• Est. Priority Date: 03/10/2014
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Ancona, Rocco, Schuckle, Richard William, Nix, William D. T.
• Primary Examiner(s): Goddard, Tammy Paige
• Assistant Examiner(s): Leland, III, Edwin S
• Application Number:
  US14/202,190
• Publication Number:
  US 20150255070A1
• Time in Patent Office: 1,156 Days
• Field of Search: 704275
• CPC Class Codes: G10L 15/08 Speech classification or search
• CPC Class Codes: G10L 15/22 Procedures used during a speech recognition process, e.g. man-machine dialogue
• CPC Class Codes: G10L 15/28 Constructional details of speech recognition systems
• CPC Class Codes: G10L 2015/088 Word spotting
• CPC Class Codes: G10L 2015/223 Execution procedure of a spoken command

Abstract

Systems and methods for managing wake-on-voice buffer quality based on system boot profiling. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include at least one logic circuit and at least one memory circuit coupled to the at least one logic circuit, the at least one memory including program instructions stored thereon that, upon execution by the at least one logic circuit, cause the IHS to: determine an expected time duration of a future wake event; receive a verbal command from a user, the verbal command configured to trigger the future wake event; capture the verbal command as an audio signal; adjust at least one of: a quality of the audio signal or a duration of the audio signal, where the adjustment is based, at least in part, upon the expected time duration; and store the adjusted audio signal in a fixed-size buffer.

Claims

1. An Information Handling System (IHS), comprising:

at least one logic circuit; and

at least one memory circuit coupled to the at least one logic circuit, the at least one memory circuit including program instructions stored thereon that, upon execution by the at least one logic circuit, cause the IHS to;

(a) while in a wake state;

identify a target sleep state to be entered into by the IHS when the IHS leaves the wake state;

estimate a time duration of a transition from the target sleep state back to the wake state, wherein the transition starts at a time an audio signal is detected and ends at a later time when an Operating System (OS) is ready for speech recognition processing; and

set a quality parameter of the audio signal to be detected based upon the estimated time duration of the transition; and

(b) enter the target sleep state;

(c) trigger the transition in response to detecting the audio signal; and

(d) store the audio signal in a fixed-size buffer.

2. The IHS of claim 1, wherein the at least one logic circuit includes a Digital Signal Processor (DSP).

3. The IHS of claim 1, wherein the wake state consumes more power than the target sleep state.

4. The IHS of claim 1, wherein the audio signal includes a keyword.

5. The IHS of claim 4, wherein the audio signal includes an instruction following the keyword, the instruction configured to be executed by the IHS during the wake state.

6. The IHS of claim 1, wherein to estimate the time duration of the transition from the target sleep state back to the wake state, the program instructions, upon execution by the at least one logic circuit, further cause the IHS to create a profile of historical wake times between the target sleep state and the wake state for different instances of the transition.

7. The IHS of claim 6, wherein the time duration of the transition from the target sleep state back to the wake state changes over time, and wherein estimating the time duration includes estimating the change.

8. The IHS of claim 1, wherein to set the quality parameter of the audio signal to be captured, the program instructions, upon execution by the at least one logic circuit, further cause the IHS to set at least one of:

a codec of the audio signal to be captured, a compression of the audio signal to be captured, a sample rate of the audio signal to be captured, a bit depth of the audio signal to be captured, or a number of channels of the audio signal to be captured.

9. In an Information Handling System (IHS), a method comprising:

while the IHS is in a wake state, identifying, at least in part by a processor within the IHS, a target sleep state to be entered into when the IHS leaves the wake state;

estimating, at least in part by the processor, a time duration of a transition from the target sleep state back to the wake state, wherein the transition starts at a time an audio signal is detected and ends at a later time when an Operating System (OS) is ready for speech recognition processing, and wherein the time duration of the transition changes across different instances of the transition; and

prior to entering the target sleep state, setting, at least in part by the processor, a quality parameter of the audio signal to be detected based at least in part upon the estimated time duration of the transition.

10. The method of claim 9, wherein the wake state consumes more power than the target sleep state.

11. The method of claim 9, wherein the audio signal includes an instruction following the keyword, the instruction configured to be executed by the IHS during the wake state.

12. The method of claim 9, further comprising creating a profile of historical wake times between the target sleep state and the wake state for different instances of the transition.

13. The method of claim 9, wherein setting the quality of the audio signal further comprises setting a codec of the audio signal, a compression of the audio signal, a sample rate of the audio signal, a bit depth of the audio signal, or a number of channels of the audio signal.

14. A memory storage device having program instructions stored thereon that, upon execution by an Information Handling System (IHS), cause the IHS to:

while the IHS is in a wake state, identify a target sleep state to be entered into when the IHS leaves the wake state;

estimate a time duration of a transition from the target sleep state back to the wake state, wherein the transition starts at a time an audio signal is detected and ends at a later time when an Operating System (OS) is ready for speech recognition processing, and wherein the time duration of the transition changes across different instances of the transition; and

prior to entering the target sleep state, set a quality parameter of the audio signal to be detected based at least in part upon the estimated time duration of the transition.

15. The memory storage device of claim 14, wherein the wake state consumes more power than the target sleep state.

16. The memory storage device of claim 14, wherein the audio signal includes an instruction following keyword, the instruction configured to be executed by the IHS during the wake state.

17. The memory storage device of claim 14, wherein the program instructions, upon execution by the IHS, further cause the IHS to create a profile of historical wake times between the target sleep state and the wake state for different instances of the transition.

18. The memory storage device of claim 14, wherein the program instructions, upon execution by the IHS, further cause the IHS to change a codec of the audio signal, a compression of the audio signal, a sample rate of the audio signal, a bit depth of the audio signal, or a number of channels of the audio signal.