Semiconductor memory having volatile and multi-bit non-volatile functionality and method of operating

• US 9,646,693 B2
• Filed: 12/22/2015
• Issued: 05/09/2017
• Est. Priority Date: 04/08/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US14/978,956
• Publication Number:
  US 20160111158A1
• Time in Patent Office: 504 Days
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

Claims

1. A semiconductor memory cell comprising:

a substrate having a first conductivity type;

a first region embedded in the substrate at a first location of the substrate and having a second conductivity type;

a second region embedded in the substrate at a second location of the substrate and having the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data as volatile memory;

a trapping layer positioned in between the first and second locations and above a surface of the substrate, the trapping layer comprising first and second storage locations configured to store data as nonvolatile memory independently of one another; and

wherein said floating body is configured to be charged to a level indicative of a state of the memory cell based on charge stored in said one of said first and second storage locations in said trapping layer, upon restoration of power to said memory cell so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.

2. The semiconductor memory cell of claim 1, wherein said memory cell functions as volatile memory upon said restoration of power to said memory cell.

3. The semiconductor memory cell of claim 1, wherein said floating body is configured to a predetermined state prior to being charged based on charge stored in said one of said first and second storage locations in said trapping layer.

4. The semiconductor memory cell of claim 1, further comprising a control gate positioned above said trapping layer.

5. The semiconductor memory cell of claim 1, wherein the semiconductor memory cell functions as a binary cell.

6. The semiconductor memory cell of claim 1, wherein the semiconductor memory cell functions as a multi-level cell.

7. A semiconductor memory cell comprising:

a substrate having a first conductivity type;

a first region embedded in the substrate at a first location of the substrate and having a second conductivity type;

a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data as volatile memory;

a trapping layer positioned in between the first and second locations and above a surface of the substrate, the trapping layer comprising first and second storage locations configured to store data as nonvolatile memory independently of one another; and

wherein charge flow into said floating body upon restoration of power to said memory cell depends on charge stored in said one of said first and second storage locations in said trapping layer so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.

8. The semiconductor memory cell of claim 7, wherein said memory cell functions as volatile memory upon said restoration of power to said memory cell.

9. The semiconductor memory cell of claim 7, wherein said floating body is configured to a predetermined state prior to being charged based on charge stored in said one of said first and second storage locations in said trapping layer.

10. The semiconductor memory cell of claim 7, further comprising a control gate positioned above said trapping layer.

11. The semiconductor memory cell of claim 7, wherein the semiconductor memory cell functions as a binary cell.

12. The semiconductor memory cell of claim 7, wherein the semiconductor memory cell functions as a multi-level cell.

13. A memory array comprising a plurality of rows and columns of semiconductor memory cells, a plurality of said cells each comprising:

a floating body region to store charge as volatile memory;

first and second regions;

a trapping layer positioned in between the first and second locations and above a surface of the floating body region;

the trapping layer comprising first and second storage locations being configured to store charge as nonvolatile memory independently of one another;

wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on charge stored in said one of said first and second storage locations in said trapping layer, upon restoration of power to said memory cell so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.

14. The semiconductor memory array of claim 13, wherein said memory cell functions as volatile memory upon said restoration of power to said memory cell.

15. The semiconductor memory array of claim 13, wherein said floating body is configured to a predetermined state prior to being charged based on charge stored in said one of said first and second storage locations in said trapping layer.

16. The semiconductor memory array of claim 13, wherein said cells further comprise control gates positioned above said trapping layers, respectively.

17. The semiconductor memory array of claim 13, wherein the semiconductor memory array functions as a binary cell memory array.

18. The semiconductor memory array of claim 13, wherein the semiconductor memory array functions as a multi-level cell memory array.