Low-noise low-distortion signal acquisition circuit and method with reduced area utilization

• US 9,646,715 B2
• Filed: 03/12/2015
• Issued: 05/09/2017
• Est. Priority Date: 01/21/2014
• Status: Active Grant

• Current Assignee: Frontgrade Colorado Springs LLC (Frontgrade Technologies Incorporated)
• Original Assignee: Aeroflex Colorado Springs Incorporated (Cobham PLC)
• Inventors: Zanchi, Alfio, Hisano, Shinichi
• Primary Examiner(s): Jager, Ryan
• Application Number:
  US14/656,177
• Publication Number:
  US 20150206600A1
• Time in Patent Office: 789 Days
• Field of Search: 327 91- 96
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H01L 31/02002 Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H03F 1/08 Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements wide-band amplifiers with inter-stage coupling networks incorporating these impedances H03F1/42
• CPC Class Codes: H03F 1/083 in transistor amplifiers H03F1/10 - H03F1/22 take precedence
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/156 One or more switches are realised in the feedback circuit of the amplifier stage
• CPC Class Codes: H03F 2200/45 the load of the amplifier being a capacitive element, e.g. CRT
• CPC Class Codes: H03F 2203/45444 the CMCL comprising a sample and hold circuit
• CPC Class Codes: H03F 2203/45514 the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/08 controlled by light
• CPC Class Codes: H03F 3/087 with IC amplifier blocks H03F3/085 takes precedence
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03M 1/1215 using time-division multiplexing

Abstract

A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

Claims

1. A sample and hold amplifier comprising:

an input node for receiving an input current signal;

a non-linear sampling capacitor circuit having an input coupled to the input node comprising a non-linear capacitor coupled between an intermediate node and ground;

an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal; and

a linear capacitor circuit coupled between the negative input and the output of the operational amplifier.

2. The sample and hold amplifier according to claim 1 wherein the non-linear sampling capacitor circuit further comprises:

a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal; and

a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal, and

wherein the linear capacitor circuit comprises a linear capacitor coupled directly between the negative input and the output of the operational amplifier.

3. The sample and hold amplifier according to claim 1 wherein the non-linear sampling capacitor circuit further comprises:

a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and

wherein the linear capacitor circuit comprises;

a linear capacitor coupled between a second intermediate node and the negative input of the operational amplifier; and

a second switch coupled between the output of the operational amplifier and the second intermediate node, in series connection with the linear capacitor.

4. The sample and hold amplifier according to claim 3 wherein the second switch is configured to switch according to the second phase signal.

5. The sample and hold amplifier according to claim 1 wherein the input current signal is provided by a photodiode.

6. A sample and hold circuit comprising a plurality of parallel sampling channels operatively coupled together, each sampling channel including a sample and hold amplifier having a switched non-linear capacitor circuit operatively coupled to a linear feedback capacitor circuit, the non-linear capacitor circuit comprising a non-linear capacitor coupled between an intermediate node and ground.

7. The sample and hold circuit of claim 6 further comprising a plurality of analog to digital converters respectively coupled to an output of each sampling channel.

8. The sample and hold circuit of claim 7 further comprising a First-In First-Out digital queue circuit (FIFO) coupled to a digital output of the analog to digital converter in each sampling channel.

9. The sample and hold circuit of claim 8 wherein the FIFO is coupled to the analog to digital converters through a multi-bit parallel bus.

10. The sample and hold circuit of claim 8 wherein the FIFO comprises a multi-bit parallel bus output.

11. The sample and hold circuit of claim 6 further comprising a multiplexer having multiple inputs respectively coupled to an analog output of each sampling channel.

12. The sample and hold circuit of claim 11 further comprising an analog to digital converter having an input coupled to an output of the multiplexer.

13. The sample and hold circuit of claim 12 wherein the analog to digital converter comprises a multi-bit parallel bus output.

14. A sample and hold circuit comprising a plurality of parallel sampling channels operatively coupled together, each sampling channel comprising:

an input node for receiving an input current signal;

a non-linear sampling capacitor circuit having an input coupled to the input node comprising a non-linear capacitor coupled between an intermediate node and ground;

an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal; and

a linear capacitor circuit coupled between the negative input and the output of the operational amplifier.

15. The sample and hold circuit according to claim 14 wherein the non-linear sampling capacitor circuit further comprises:

a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal; and

a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal, and

wherein the linear capacitor circuit comprises a linear capacitor coupled directly between the negative input and the output of the operational amplifier.

16. The sample and hold circuit according to claim 14 wherein the non-linear sampling capacitor circuit further comprises:

a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal; and

wherein the linear capacitor circuit comprises;

a linear capacitor coupled between a second intermediate node and the negative input of the operational amplifier;

a second switch coupled between the output of the operational amplifier and the second intermediate node, in series connection with the linear capacitor.

17. The sample and hold circuit according to claim 16 wherein the second switch is configured to switch according to the second phase signal.

18. The sample and hold circuit according to claim 14 wherein the input current signal is provided by a photodiode.