Method of manufacturing a semiconductor heteroepitaxy structure

• US 9,647,094 B2
• Filed: 08/02/2013
• Issued: 05/09/2017
• Est. Priority Date: 08/02/2013
• Status: Active Grant

• Current Assignee: University Of Kentucky Research Foundation (University of Kentucky)
• Original Assignee: University Of Kentucky Research Foundation (University of Kentucky)
• Inventors: Chen, Zhi David
• Primary Examiner(s): GONDARENKO, NATALIA A
• Application Number:
  US13/957,480
• Publication Number:
  US 20150037930A1
• Time in Patent Office: 1,376 Days
• Field of Search: 438104, 438591, 438299, 438503, 257288, 257411, 257E2119, 257E2109, 257E21444, 257E29242, 257E29255
• CPC Class Codes: H01L 21/3221 of silicon bodies, e.g. for gettering
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365

Abstract

A method of manufacturing a semiconductor structure includes the steps of depositing a layer of semiconductor oxide on a base semiconductor layer, scavenging oxygen from the layer of semiconductor oxide and recrystallizing the oxygen scavenged layer of semiconductor oxide as a semiconductor heteroepitaxy layer.

Claims

1. A method of manufacturing a semiconductor heteroepitaxy structure, comprising forming a structure precursor by:

(a) depositing ex situ a layer of semiconductor silicon oxide on a base semiconductor substrate layer, wherein said base semiconductor substrate layer comprises a III-V semiconductor with native oxides, wherein thickness of the layer of silicon oxide is less than 1.5 nm;

(b) depositing ex situ a layer of oxygen-permeable insulator on said layer of silicon oxide, wherein the layer of oxygen-permeable insulator comprises hafnium oxide;

(c) depositing ex situ a layer of oxygen-gettering metal onto said insulator layer, wherein said layer of oxygen-gettering material is hafnium, titanium or mixtures thereof;

(d) depositing ex situ a layer of gate metal or a protecting dielectric material comprising a titanium nitride-polysilicon mixture on said layer of oxygen-gettering metal, said layer of gate metal or said protecting dielectric material deposited to protect said oxygen-gettering metal from oxidation caused by oxygen diffusing from ambient air, thereby forming the structure precursor; and

annealing the structure precursor at a predetermined temperature so that (1) oxygen atoms from said silicon oxide layer are scavenged, moved to and reacted with said layer of oxygen-gettering metal and (2) silicon atoms in the scavenged layer are rearranged and crystallized to form a strained, silicon epitaxy film on said base semiconductor substrate layer, thereby removing the native oxides and providing the semiconductor heteroepitaxy structure.

2. The method of claim 1, including using atomic layer deposition to deposit said layer of silicon oxide.

3. The method of claim 1, including using chemical vapor deposition to deposit said layer of silicon oxide.

4. The method of claim 1, including using a material selected from a group consisting of InGaAs, GaAs, InAs, InSb, InGaSb, InAsSb, GaN, InGaN, GaP, InGaP, and mixtures thereof for said base semiconductor substrate layer.

5. The method of claim 1, including completing said annealing at said predetermined temperature of between 300 to 1000°

C. for a time of between 1 to 600 seconds.

6. The method of claim 1, wherein said layer of silicon oxide has a thickness of between 0.5 nm and 10 nm.

7. The method of claim 6, wherein said base semiconductor substrate layer has a thickness of between 100 μ

m and 600 μ

m.

8. The method of claim 7, wherein said insulator layer has a thickness of between 1 nm and 10 nm.

9. The method of claim 8, wherein said oxygen-gettering layer has a thickness of between 1 nm and 100 nm.

10. The method of claim 9, wherein said gate metal layer has a thickness of between 80 nm and 200 nm.

11. The method of claim 10, wherein said strained, silicon epitaxy film has a thickness of between 0.2 nm and 5 nm.

12. The method of claim 1, wherein said gate metal layer has a thickness of between 80 nm and 200 nm.

13. The method of claim 1, wherein said layer of oxygen-gettering metal and said gate metal layer are selected from different metals.