Semiconductor device and method for manufacturing the same

• US 9,647,095 B2
• Filed: 02/16/2016
• Issued: 05/09/2017
• Est. Priority Date: 10/17/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Suzawa, Hideomi
• Primary Examiner(s): Ingham, John C
• Application Number:
  US15/044,422
• Publication Number:
  US 20160163839A1
• Time in Patent Office: 448 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device formed using an oxide semiconductor layer and having small electrical characteristic variation is provided. A highly reliable semiconductor device including an oxide semiconductor layer and exhibiting stable electric characteristics is provided. Further, a method for manufacturing the semiconductor device is provided. In the semiconductor device, an oxide semiconductor layer is used for a channel formation region, a multilayer film which includes an oxide layer in which the oxide semiconductor layer is wrapped is provided, and an edge of the multilayer film has a curvature in a cross section.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first oxide layer;

forming an oxide semiconductor layer over the first oxide layer;

forming a second oxide layer over the oxide semiconductor layer;

forming a resist mask over the second oxide layer;

performing first etching on the second oxide layer and the oxide semiconductor layer using the resist mask whereby each of the second oxide layer and the oxide semiconductor layer is processed into an island shape; and

performing second etching on the first oxide layer whereby the first oxide layer is processed into an island shape,

wherein a reaction product generated in the second etching is attached onto a side surface of the oxide semiconductor layer processed into the island shape whereby a third oxide layer is formed on the side surface of the oxide semiconductor layer.

2. The method for manufacturing a semiconductor device according to claim 1,

wherein heat treatment is performed in an oxidation gas atmosphere after the resist mask is removed.

3. The method for manufacturing a semiconductor device according to claim 1,

wherein the oxide semiconductor layer, the first oxide layer, the second oxide layer and the third oxide layer contain at least indium, and

wherein the oxide semiconductor layer has a higher proportion of indium than the first oxide layer, the second oxide layer and the third oxide layer.

4. The method for manufacturing a semiconductor device according to claim 1,

wherein each of the first oxide layer, the second oxide layer and the third oxide layer has a larger energy gap than the oxide semiconductor layer.

5. The method for manufacturing a semiconductor device according to claim 1,

wherein a thickness of the third oxide layer is larger than a thickness of the second oxide layer.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first oxide layer;

forming an oxide semiconductor layer over the first oxide layer;

forming a second oxide layer over the oxide semiconductor layer;

forming a resist mask over the second oxide layer;

performing first etching on the second oxide layer and the oxide semiconductor layer using the resist mask whereby each of the second oxide layer and the oxide semiconductor layer is processed into an island shape; and

performing second etching on the first oxide layer whereby the first oxide layer is processed into an island shape,

wherein a reaction product generated in the second etching is attached onto a side surface of the oxide semiconductor layer processed into the island shape whereby a third oxide layer is formed on the side surface of the oxide semiconductor layer,

wherein a side surface of the third oxide layer in a cross section has a curvature, and

wherein a total thickness of the first oxide layer, the oxide semiconductor layer, and the second oxide layer is greater than or equal to 1/50 and less than or equal to 50 times as large as a curvature radius of the side surface of the third oxide layer.

7. The method for manufacturing a semiconductor device according to claim 6,

wherein heat treatment is performed in an oxidation gas atmosphere after the resist mask is removed.

8. The method for manufacturing a semiconductor device according to claim 6,

wherein the oxide semiconductor layer, the first oxide layer, the second oxide layer and the third oxide layer contain at least indium, and

wherein the oxide semiconductor layer has a higher proportion of indium than the first oxide layer, the second oxide layer and the third oxide layer.

9. The method for manufacturing a semiconductor device according to claim 6,

wherein each of the first oxide layer, the second oxide layer and the third oxide layer has a larger energy gap than the oxide semiconductor layer.

10. The method for manufacturing a semiconductor device according to claim 6,

wherein a thickness of the third oxide layer is larger than a thickness of the second oxide layer.