Oxide semiconductor, thin film transistor, and display device

• US 9,647,137 B2
• Filed: 08/11/2015
• Issued: 05/09/2017
• Est. Priority Date: 10/24/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ito, Shunichi, Sasaki, Toshinari, Hosoba, Miyuki, Sakata, Junichiro
• Primary Examiner(s): McCall Shepard, Sonya D
• Application Number:
  US14/822,995
• Publication Number:
  US 20150380566A1
• Time in Patent Office: 637 Days
• Field of Search: 257 43, 257 59, 257 72, 257E27111, 257E29117
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO₃(ZnO)_m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.

Claims

1. A semiconductor device comprising:

a substrate;

a gate electrode on the substrate;

a first silicon nitride insulating layer on and in contact with the gate electrode;

a first silicon oxide insulating layer on and in contact with the first silicon nitride insulating layer;

an oxide semiconductor layer on and in contact with the first silicon oxide insulating layer;

a source electrode and a drain electrode each in contact with the oxide semiconductor layer; and

a second silicon oxide insulating layer on and in contact with the oxide semiconductor layer in a region overlapping with the gate electrode,

wherein the second silicon oxide insulating layer is on and in contact with the source electrode and the drain electrode, and

wherein every point where the oxide semiconductor layer is in contact with one of the source electrode and the drain electrode overlaps with the gate electrode.

4. The semiconductor device according to claim 1,

wherein every point where the oxide semiconductor layer is in contact with the other one of the source electrode and the drain electrode overlaps with the gate electrode.

7. The semiconductor device according to claim 1,

wherein a channel region of the oxide semiconductor layer totally overlaps with the gate electrode.

10. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

13. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer has an amorphous structure.

16. The semiconductor device according to claim 1,

wherein the source electrode and the drain electrode are in contact with a bottom surface of the oxide semiconductor layer.

19. The semiconductor device according to claim 1,

wherein the source electrode and the drain electrode are in contact with a top surface of the oxide semiconductor layer.

22. The semiconductor device according to claim 1,

wherein the source electrode and the drain electrode are in contact with a top surface of the oxide semiconductor layer, and

wherein the oxide semiconductor layer is thinner in a region overlapping with the gate electrode and in contact with the second silicon oxide insulating layer than in a region overlapping with the source electrode.

25. The semiconductor device according to claim 1, further comprising:

a pixel electrode in electrical contact with the oxide semiconductor layer via one of the source electrode and the drain electrode; and

a driver circuit formed on a single crystal substrate, the single crystal substrate being affixed to the substrate and the driver circuit being connected to the pixel electrode,

wherein the semiconductor device is a display device.

2. A semiconductor device comprising:

a substrate;

a gate electrode on the substrate;

a first silicon nitride insulating layer on and in contact with the gate electrode;

a first silicon oxide insulating layer on and in contact with the first silicon nitride insulating layer;

an oxide semiconductor layer on and in contact with the first silicon oxide insulating layer;

a source electrode and a drain electrode each in contact with the oxide semiconductor layer;

a second silicon oxide insulating layer on and in contact with the oxide semiconductor layer in a region overlapping with the gate electrode; and

a nitride insulating layer on and in contact with the second silicon oxide insulating layer,

wherein the second silicon oxide insulating layer is on and in contact with the source electrode and the drain electrode, and

wherein every point where the oxide semiconductor layer is in contact with one of the source electrode and the drain electrode overlaps with the gate electrode.

5. The semiconductor device according to claim 2,

wherein every point where the oxide semiconductor layer is in contact with the other one of the source electrode and the drain electrode overlaps with the gate electrode.

8. The semiconductor device according to claim 2,

wherein a channel region of the oxide semiconductor layer totally overlaps with the gate electrode.

11. The semiconductor device according to claim 2,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

14. The semiconductor device according to claim 2,

wherein the oxide semiconductor layer has an amorphous structure.

17. The semiconductor device according to claim 2,

wherein the source electrode and the drain electrode are in contact with a bottom surface of the oxide semiconductor layer.

20. The semiconductor device according to claim 2,

wherein the source electrode and the drain electrode are in contact with a top surface of the oxide semiconductor layer.

23. The semiconductor device according to claim 2,

wherein the source electrode and the drain electrode are in contact with a top surface of the oxide semiconductor layer, and

wherein the oxide semiconductor layer is thinner in a region overlapping with the gate electrode and in contact with the second silicon oxide insulating layer than in a region overlapping with the source electrode.

26. The semiconductor device according to claim 2, further comprising:

a pixel electrode in electrical contact with the oxide semiconductor layer via one of the source electrode and the drain electrode; and

a driver circuit formed on a single crystal substrate, the single crystal substrate being affixed to the substrate and the driver circuit being connected to the pixel electrode,

wherein the semiconductor device is a display device.

3. A semiconductor device comprising:

a substrate;

a gate electrode on the substrate;

a first silicon nitride insulating layer on and in contact with the gate electrode;

a first silicon oxide insulating layer on and in contact with the first silicon nitride insulating layer;

an oxide semiconductor layer on and in contact with the first silicon oxide insulating layer;

a source electrode and a drain electrode each in contact with the oxide semiconductor layer;

a second silicon oxide insulating layer on and in contact with the oxide semiconductor layer in a region overlapping with the gate electrode; and

a second silicon nitride insulating layer on and in contact with the second silicon oxide insulating layer,

wherein the second silicon oxide insulating layer is on and in contact with the source electrode and the drain electrode, and

wherein every point where the oxide semiconductor layer is in contact with one of the source electrode and the drain electrode overlaps with the gate electrode.

6. The semiconductor device according to claim 3,

wherein every point where the oxide semiconductor layer is in contact with the other one of the source electrode and the drain electrode overlaps with the gate electrode.

9. The semiconductor device according to claim 3,

wherein a channel region of the oxide semiconductor layer totally overlaps with the gate electrode.

12. The semiconductor device according to claim 3,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

15. The semiconductor device according to claim 3,

wherein the oxide semiconductor layer has an amorphous structure.

18. The semiconductor device according to claim 3,

wherein the source electrode and the drain electrode are in contact with a bottom surface of the oxide semiconductor layer.

21. The semiconductor device according to claim 3,

wherein the source electrode and the drain electrode are in contact with a top surface of the oxide semiconductor layer.

24. The semiconductor device according to claim 3,

wherein the source electrode and the drain electrode are in contact with a top surface of the oxide semiconductor layer, and

wherein the oxide semiconductor layer is thinner in a region overlapping with the gate electrode and in contact with the second silicon oxide insulating layer than in a region overlapping with the source electrode.

27. The semiconductor device according to claim 3, further comprising:

a pixel electrode in electrical contact with the oxide semiconductor layer via one of the source electrode and the drain electrode; and

a driver circuit formed on a single crystal substrate, the single crystal substrate being affixed to the substrate and the driver circuit being connected to the pixel electrode,

wherein the semiconductor device is a display device.