Encapsulated molded package with embedded antenna for high data rate communication using a dielectric waveguide

• US 9,647,329 B2
• Filed: 12/30/2014
• Issued: 05/09/2017
• Est. Priority Date: 04/09/2014
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Herbsommer, Juan Alejandro, Romig, Matthew David
• Primary Examiner(s): Nguyen, Hoang
• Application Number:
  US14/585,724
• Publication Number:
  US 20150295305A1
• Time in Patent Office: 861 Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45565 Single coating layer
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/495 : Lead-frames or other flat leads H01L23/498 takes precedence; lead frame interconnections between components H01L23/52
• CPC Class Codes: H01L 23/49517 : Additional leads
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1421 : RF devices
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H01Q 1/40 : Radiating elements coated with or embedded in protective material
• CPC Class Codes: H01Q 19/108 : Combination of a dipole with a plane reflecting surface H01Q19/106 takes precedence; strip line H01Q9/065
• CPC Class Codes: H01Q 9/0407 : Substantially flat resonant element parallel to ground plane, e.g. patch antenna dipole H01Q9/285; monopole H01Q9/40
• CPC Class Codes: H01Q 9/16 : with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole H01Q9/44 takes precedence

Abstract

An encapsulated integrated circuit has transceiver circuitry operable to produce and/or receive a radio frequency (RF) signal, wherein bond pads on the IC die are coupled to the transceiver input/output (IO) circuitry. An antenna structure is coupled to the IO circuitry via the bond pads. Mold material encapsulates the IC die and the antenna structure, wherein the antenna structure is positioned so as to be approximately in alignment with a core of a dielectric waveguide positioned adjacent the encapsulated IC.

Claims

1. An electronics system comprising an encapsulated integrated circuit, the encapsulated integrated circuit comprising:

a lead frame;

an integrated circuit (IC) chip mounted on the lead frame, the IC chip having transceiver circuitry operable to produce and/or receive a radio frequency (RF) signal, wherein bond pads on the IC chip are coupled to the transceiver input/output (IO) circuitry;

an antenna structure coupled to the IO circuitry via the bond pads; and

mold material encapsulating the IC chip and the antenna structure, wherein the antenna structure is positioned so as to be adjacent an interface edge of the encapsulated IC chip;

wherein the antenna structure comprises a radiating element on one surface of a substrate and a reflector element on an opposite surface of the substrate.

2. The encapsulated IC of claim 1, wherein the antenna structure is mounted parallel to and in close proximity to the interface edge of the encapsulated IC package.

3. The encapsulated IC of claim 1, wherein the antenna structure is mounted perpendicular to and in close proximity or exposed to the interface edge of the encapsulated IC package.

4. The encapsulated IC of claim 3, wherein one end of the antenna structure is coupled to and supported by bond pads on the IC and the other end of the antenna structure is supported only by the mold material.

5. The encapsulated IC of claim 3, wherein one end of the antenna structure is coupled to and supported by bond pads on the lead frame and the other end of the antenna structure is supported only by the mold material.

6. An electronics system comprising an encapsulated integrated circuit, the encapsulated integrated circuit comprising:

a lead frame;

an integrated circuit (IC) chip mounted on the lead frame, the IC chip having transceiver circuitry operable to produce and/or receive a radio frequency (RF) signal, wherein bond pads on the IC chip are coupled to the transceiver input/output (IO) circuitry;

an antenna structure coupled to the IO circuitry via the bond pads; and

mold material encapsulating the IC chip and the antenna structure, wherein the antenna structure is positioned so as to be adjacent an interface edge of the encapsulated IC chip;

a substrate having a top surface, wherein the encapsulated IC is mounted on the top surface of the substrate; and

a dielectric waveguide (DWG) formed on the top surface of the substrate with an end of the DWG adjacent to the interface edge of the encapsulate IC;

wherein the DWG has a second antenna structure embedded in the end of the DWG.

7. A method for fabricating an integrated circuit, the method comprising:

forming a lead frame strip;

mounting a plurality of integrated circuit (IC) chips on the lead frame, wherein the plurality of IC chips are arranged as pairs such that one IC chip in each pair is rotated 180 degrees with respect to an adjacent IC chip in the pair;

coupling an antenna structure between each pair of IC chips;

encapsulating the lead frame strip, plurality of IC chips, and antenna structures with a molding compound; and

singulating the encapsulated lead frame strip to form a plurality of encapsulated IC chips, such that each antenna structure is cut in half at an interface edge of the plurality of encapsulated ICs.

8. The method of claim 7, further comprising selecting the molding compound to have a dielectric value that is within a range of 15-60.

9. The method of claim 7, wherein the antenna structure is one or more bond wires, and wherein coupling the antenna structure between each pair of IC chips comprises attaching one end of the bond wire to a bond pad on one of the pair of ICs, and attaching an opposite end of the bond wire to a bond pad on the other one of the pair of ICs.

10. The method of claim 7, wherein the antenna structure is a substrate, and wherein coupling the antenna structure between each pair of IC chips comprises coupling one end of the substrate to a bond pad on one of the pair of ICs, and coupling an opposite end of the substrate to a bond pad on the other one of the pair of ICs.

11. The method of claim 7, further comprising:

mounting at least one of the encapsulated ICs on a surface of substrate; and

forming a dielectric waveguide (DWG) on the surface of the substrate using an additive process, wherein an antenna is formed by the additive process in an end of the DWG adjacent the interface edge of the encapsulated IC.