Integrated bias supply, reference and bias current circuits for GaN devices

• US 9,647,476 B2
• Filed: 03/24/2015
• Issued: 05/09/2017
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel M., Sharma, Santosh, Zhang, Ju Jason
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Tiku, Sisay G
• Application Number:
  US14/667,531
• Publication Number:
  US 20160079853A1
• Time in Patent Office: 777 Days
• Field of Search: 323271-274
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 1/0048 : Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 3/157 : with digital control
• CPC Class Codes: H02M 3/1584 : with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 : Interface arrangements
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 : using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: Y02B 40/00 : Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Claims

1. A power supply circuit comprising:

a circuit element;

a voltage-limited voltage or current source, the voltage or current source comprising a GaN-based depletion mode transistor having a gate, a source, and a drain, wherein the GaN-based depletion mode transistor is configured to selectively allow current to flow through the circuit element such that when the GaN-based depletion mode transistor allows current to flow through the circuit element, a voltage at the source of the GaN-based depletion mode transistor is limited by;

a voltage at the gate of the GaN-based depletion mode transistor, and

a pinch-off voltage of the GaN-based depletion mode transistor,

wherein the GaN-based depletion-mode transistor is configured to set a reference voltage, and wherein the drain of the GaN-based depletion-mode transistor is coupled to a first power source;

a plurality of series connected circuit elements coupled between the source of the GaN-based depletion mode transistor and a second node;

one or more intermediate nodes disposed between each of the plurality of series connected circuit elements; and

a GaN-based reference voltage transistor having a second gate connected to one of the one or more intermediate nodes, a second source configured to deliver power to a circuit and a second drain connected to a second power source,

wherein the GaN-based reference voltage transistor includes one or more diodes or diode-connected transistors disposed between the second gate and the second source, configured as gate overvoltage protection devices.

2. The power supply circuit of claim 1, wherein the gate of the depletion-mode transistor is connected to a ground.

3. The power supply circuit of claim 1, wherein the gate of the depletion-mode transistor is formed by a metal layer disposed over a passivation layer.

4. The power supply circuit of claim 1, wherein the depletion-mode transistor is disposed on a GaN-based power integrated circuit device.

5. The power supply circuit of claim 1, further comprising a disable circuit configured to prevent the second source from delivering power.

6. The power supply circuit of claim 1, wherein the reference voltage transistor is a GaN-based enhancement-mode transistor.

7. The power supply circuit of claim 1, configured to be a ground referenced power supply in a half bridge circuit.

8. The power supply circuit of claim 1, wherein the second node is connected to ground.

9. The power supply circuit of claim 1, wherein the source of the depletion mode transistor is coupled to a first node, and wherein a capacitor is connected between the first node and the second node.

10. The power supply circuit of claim 1, wherein the source of the depletion mode transistor is coupled to a first node, and wherein at least one of the first node and the second node are connected to a capacitor.

11. The power supply circuit of claim 1, wherein the source of the depletion mode transistor is coupled to a first node, and wherein a diode or a diode-connected transistor is coupled between the first node and a circuit configured to deliver power.

12. The power supply circuit of claim 1, wherein the first power source comprises a floating voltage.

13. The power supply circuit of claim 1, wherein the reference voltage transistor is configured to deliver the power only when the first power source has a voltage within a predetermined range.

14. The power supply circuit of claim 1, wherein the first power source has a constantly varying voltage.

15. The power supply circuit of claim 14 wherein the first power source is an AC line voltage.

16. The power supply circuit of claim 1, further comprising a third enhancement-mode transistor having a third gate, a third source and a third drain;

a fourth enhancement-mode transistor having a fourth gate, a fourth source and a fourth drain;

wherein the third and the fourth sources are coupled to a third node, the third gate and fourth gates are coupled together, the third drain is coupled to the second node and the fourth drain is coupled to a reference current sink terminal.

17. The power supply circuit of claim 16 further comprising a comparator circuit coupled to a ground referenced power supply and the reference current sink terminal.

18. A power supply circuit comprising:

a circuit element;

a voltage-limited voltage or current source, the voltage or current source comprising a GaN-based depletion mode transistor having a gate, a source, and a drain, wherein the GaN-based depletion mode transistor is configured to selectively allow current to flow through the circuit element such that when the GaN-based depletion mode transistor allows current to flow through the circuit element, a voltage at the source of the GaN-based depletion mode transistor is limited by;

a voltage at the gate of the GaN-based depletion mode transistor, and

a pinch-off voltage of the GaN-based depletion mode transistor,

wherein the GaN-based depletion-mode transistor is configured to set a reference voltage, and wherein the drain of the GaN-based depletion-mode transistor is coupled to a first power source;

a plurality of series connected circuit elements coupled between the source of the GaN-based depletion mode transistor and a second node;

one or more intermediate nodes disposed between each of the plurality of series connected circuit elements;

a third enhancement-mode transistor having a third gate, a third source and a third drain;

a fourth enhancement-mode transistor having a fourth gate, a fourth source and a fourth drain,

wherein the third and the fourth sources are coupled to a third node, the third gate and fourth gates are coupled together, the third drain is coupled to the second node, and the fourth drain is coupled to a reference current sink terminal.

19. The power supply circuit of claim 18, wherein the gate of the depletion-mode transistor is connected to a ground.

20. The power supply circuit of claim 18, wherein the gate of the depletion-mode transistor is formed by a metal layer disposed over a passivation layer.

21. The power supply circuit of claim 18, wherein the depletion-mode transistor is disposed on a GaN-based power integrated circuit device.

22. The power supply circuit of claim 18, further comprising a reference voltage transistor comprising a second gate connected to one of the one or more intermediate nodes, a second source configured to deliver current to another circuit at a regulated voltage, and a second drain connected to the source of the depletion mode transistor.

23. The power supply circuit of claim 22, wherein the reference voltage transistor includes one or more diodes or diode-connected transistors disposed between the second gate and the second source, configured as gate overvoltage protection devices.

24. The power supply circuit of claim 22, further comprising a disable circuit configured to prevent the reference voltage transistor from delivering current to the other circuit.

25. The power supply circuit of claim 22, wherein the reference voltage transistor is a GaN-based enhancement-mode transistor.

26. The power supply circuit of claim 22, wherein the reference voltage transistor is configured to deliver current to the other circuit only when the first power source has a voltage within a predetermined range.

27. The power supply circuit of claim 18, configured to be a ground referenced power supply in a half bridge circuit.

28. The power supply circuit of claim 18, wherein the source of the depletion mode transistor is coupled to a first node, and wherein a capacitor is connected between the first node and the second node.

29. The power supply circuit of claim 18, wherein the source of the depletion mode transistor is coupled to a first node, and wherein at least one of the first node and the second node are connected to a capacitor.

30. The power supply circuit of claim 18, wherein the source of the depletion mode transistor is coupled to a first node, and wherein a diode or a diode-connected transistor is coupled between the first node and a circuit configured to deliver power.

31. The power supply circuit of claim 18, wherein the first power source comprises a floating voltage.

32. The power supply circuit of claim 18, wherein the first power source has a constantly varying voltage.

33. The power supply circuit of claim 18, wherein the first power source is an AC line voltage.

34. The power supply circuit of claim 18, further comprising a comparator circuit coupled to a ground referenced power supply and the reference current sink terminal.