High voltage generation using low voltage devices

• US 9,647,536 B2
• Filed: 07/28/2015
• Issued: 05/09/2017
• Est. Priority Date: 07/28/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Reddy, Gooty Sukumar, Kumar, Potnuru Venkata Pradeep, Yadala, Sridhar
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US14/811,314
• Publication Number:
  US 20170033682A1
• Time in Patent Office: 651 Days
• Field of Search: 36518909, 365226
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A charge pump design suitable for generating high voltages employs multiple low voltage capacitors and low voltage transfer switches, with a limited number of high voltage devices. This is designed such that during a first clock phase, capacitors are each connected between an input voltage and ground and, during a second clock phase all the capacitors are connected in series to generate the required voltage. Both the switches (PMOS) and as well the capacitors are realized as low voltage devices. The ability to use low voltage devices can significantly reduce the area and also a reduction in current consumption relative to the usual high voltage charge pumps which uses high voltage devices.

Claims

1. A charge pump system, comprising:

a first charge pump section connected to receive an input voltage and a first clock signal, including;

three or more capacitors, each capacitor having a first plate and a second plate; and

switching circuitry connected to receive the first clock signal, whereby the capacitors are alternately connectable according to the first clock signal in a first phase and a second phase,

wherein, in the first phase, the first plate of each of the capacitors is connected to receive the input voltage and the second plate of each of the capacitors is connected to ground, and

wherein, in the second phase, the capacitors are connected in series such that the second plate of a first capacitor in the series is connected to receive the input voltage, and for each capacitor after the first capacitor in the series, the second plate is connected to the first plate of a preceding capacitor in the series, and the first plate of a last capacitor in the series is connected to supply an output voltage of the first charge pump section, wherein the switching circuitry comprises;

a first number of PMOS transistors connected in series between the first plate of the first capacitor in the series and the second plate of a second capacitor in the series, and

a second number of PMOS transistors having control gates connected to the first plate of the first capacitor in the series, wherein the second number of PMOS transistors are connected in series between the first plate of the second capacitor and the second plate of a third capacitor in the series,

wherein the second number is larger than the first number.

2. The charge pump system of claim 1, wherein control gates of the first number of PMOS transistors are connected to the input voltage.

3. The charge pump system of claim 1, wherein the three or more capacitors are configured for voltage differences substantially equal to and/or less than the input voltage.

4. The charge pump system of claim 1, further comprising an initial charge pump section configured to generate the input voltage as a regulated output level of a supply voltage.

5. The charge pump system of claim 1, wherein the switching circuitry is further configured to connect the first plates of the three or more capacitors to the input voltage when the first clock signal is high.

6. The charge pump system of claim 1, further comprising:

three or more switches, each of the three or more switches being connected between the first plate of a respective one of the three of more capacitors and the input voltage; and

a level shifter configured to generate a boosted form of the first clock signal, wherein gates of the three or more switches are connected to receive the boosted form of the first clock signal.

7. The charge pump system of claim 1, wherein the second plate of the first capacitor in the series is connected to receive a boosted and inverted form of the first clock signal.

8. The charge pump system of claim 1, wherein the switching circuitry further comprises NMOS transistors configured to connect the second plate of the second capacitor in the series and the second plate of the third capacitor in the series to ground when the first clock signal is high.

9. The charge pump system of claim 1, further comprising:

regulation circuitry connected to generate the first clock signal from an input clock signal in response to a first clock enable signal, the regulation circuitry comprising;

a voltage divider circuit connected between the output voltage and ground; and

an operational amplifier configured to generate the first clock enable signal, the operational amplifier having a first input connected to a reference voltage and a second input connected to a node of the voltage divider circuit.

10. The charge pump system of claim 1, further comprising:

a low threshold voltage diode connected to the first plate of the last capacitor in the series.

11. The charge pump system of claim 1, wherein the three or more capacitors and the switching circuitry comprise peripheral elements of a non-volatile memory circuit.

12. The charge pump system of claim 1, wherein the three or more capacitors and the switching circuit comprise peripheral circuitry of a non-volatile memory, the non-volatile memory comprising a monolithic three-dimensional semiconductor memory device having memory cells arranged in multiple physical levels.

13. A method, comprising:

alternately connecting N capacitors in a first phase and a second phase according to a first clock signal by use of switching circuitry, wherein each of the N capacitors comprises a first conductor and a second conductor, wherein N is an integer greater than two, and wherein connecting the N capacitors in the first phase includes;

connecting the first conductors of the N capacitors to receive an input voltage while the second conductors of the N capacitors are connected to ground,

and wherein connecting the N capacitors in the second phase includes;

connecting the N capacitors in series from a first capacitor in the series to a last capacitor in the series, and

supplying an output voltage from the first conductor of the last capacitor in the series,

wherein connecting the N capacitors in series comprises;

connecting the first conductor of a (M−

1)st capacitor in the series and the second plate of an Mth capacitor in the series through a first number of PMOS transistors, where M is an integer between two and N; and

connecting the first plate of the Mth capacitor and the second plate of an (M+1)st capacitor in the series through a second number of PMOS transistors having control gates connected to the first plate of the (M−

1)st capacitor,

wherein the second number is larger than the first number.

14. The method of claim 13, wherein M is two and the first number of PMOS transistors have control gates connected to the input voltage.

15. The method of claim 13, wherein the N capacitors cannot support voltage differences greater than the input voltage, and wherein the PMOS transistors cannot support voltage differences greater than the input voltage.

16. The method of claim 13, further comprising generating the input voltage as a regulated output level of a supply voltage level.

17. The method of claim 13, further comprising

generating the first clock signal from an input clock signal in response to a first clock enable signal.

18. The method of claim 13, further comprising supplying the output voltage through a low threshold voltage diode connected transistor configured for voltage differences greater than the input voltage.

19. The method of claim 13, further comprising using the output voltage in one or more of a programming operation, a sensing operation, and an erase operation on the non-volatile memory.

20. The method of claim 13, wherein the capacitors and the switching circuitry are embodied within a peripheral region of a non-volatile memory, the method further comprising using the output voltage in one or more of a write operation, a program operation, a sense operation, and an erase operation on the non-volatile memory.

21. The method of claim 13, wherein the capacitors and the switching circuitry are part of a non-volatile memory circuit, the method further comprising using the output voltage in one or more of a programming operation, an erase operation, and a sensing operation on non-volatile memory cells of the non-volatile memory circuit.

22. The method of claim 13, further comprising using the output voltage as an operating voltage for a monolithic three dimensional semiconductor memory device having memory cells arranged in multiple physical levels above a silicon substrate, each memory cell including a charge storage medium.