Low power buffer with gain boost

• US 9,647,643 B2
• Filed: 08/08/2016
• Issued: 05/09/2017
• Est. Priority Date: 02/04/2015
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Inphi Corporation
• Inventors: Gorecki, James Lawrence, Tan, Han-Yuan
• Primary Examiner(s): Hernandez, William
• Application Number:
  US15/231,449
• Publication Number:
  US 20160352372A1
• Time in Patent Office: 274 Days
• Field of Search: 326 62, 326 82, 326 83, 327108, 327109, 327110, 327111, 327112, 327306, 327307, 327331, 327332, 327333
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H03F 1/3205 in field-effect transistor amplifiers
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 3/20 Automatic control H03G3/005 takes precedence; combined with volume compression or expansion H03G7/00
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 5/023 using field effect transistors
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/124 Sampling or signal conditioning arrangements specially adapted for A/D converters
• CPC Class Codes: H03M 3/38 Calibration
• CPC Class Codes: H04B 17/21 for calibration; for correcting measurements

Abstract

The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative g_ds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

Claims

1. A communication system comprising:

a clock source for providing a clock signal;

an ADC module comprising a buffer circuit, wherein the buffer circuit comprises;

a first connection node, a first supply node, a third connection node, a first current feedback node;

a first transistor coupled to the first supply node and the first connection node, the first transistor being configured to process a first input signal;

a second transistor coupled to the first connection node, the second transistor being configured to process a second input signal, the second input signal being a complement of the first input signal;

a fifth transistor coupled to the first connection node, the first supply node, and the third connection node;

a sixth transistor coupled to the first current feedback node and the third connection node;

a first bias circuit coupled to the second transistor;

a third bias circuit coupled to the sixth transistor; and

a first current mirror coupled to the first current feedback node and the first supply node.

2. The system of claim 1, wherein at least one of, the first bias circuit, or the third bias circuit, is controlled by a bias signal.

3. The system of claim 1 wherein the clock source comprises a PLL module.

4. The system of claim 1 wherein the clock source comprises a clock divider module.

5. The system of claim 1 further comprising one or more variable gain amplifiers for processing the first input signal and the second input signal.

6. The system of claim 1 wherein the ADC module further comprises a plurality of shift and hold registers.

7. The system of claim 1 further comprising a phase interpolator module.

8. The system of claim 1 wherein the ADC module further comprises a plurality of track and hold registers.

9. The system of claim 1, wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, the first bias circuit, and the third bias circuit have a respective plurality of design attributes, and wherein at least one of the respective plurality of design attributes is established to achieve a gain equal to a first target gain of one, the gain being defined by an output amplitude of a first output signal at the first connection node divided by an input amplitude of the first input signal.

10. The system of claim 1, wherein at least one of the first transistor, the second transistor, the sixth transistor, the first bias circuit, and the third bias circuit comprise an N-type MOSFET device, and wherein the fifth transistor comprises a P-type MOSFET device.

11. A buffer circuit device comprising:

a first connection node;

a third connection node;

a first supply node;

a first current feedback node;

a first transistor coupled to the first supply node and the first connection node, the first transistor being configured to process a first input signal, the first transistor comprises a MOSFET device;

a second transistor coupled to the first connection node, the second transistor being configured to process a second input signal, the second input signal being a complement of the first input signal;

a fifth transistor coupled to the first connection node, the first supply node, and the third connection node;

a sixth transistor coupled to the first current feedback node and the third connection node;

a first bias circuit coupled to the second transistor;

a third bias circuit coupled to the sixth transistor; and

a first current mirror coupled to the first current feedback node and the first supply node.

12. The device of claim 11 further comprising a first input node for receiving the first input signal and a second input node for receiving the second input signal.

13. The device of claim 12, wherein the first transistor and the sixth transistor are coupled to the first input node, and wherein the second transistor is coupled to the second input node.

14. The device of claim 11, wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, the first bias circuit, and the third bias circuit have a respective plurality of design attributes, and wherein at least one of the respective plurality of design attributes is established to achieve a gain equal to a first target gain of one, the gain being defined by an output amplitude of a first output signal at the first connection node divided by an input amplitude of the first input signal.

15. The device of claim 11, wherein at least one of the first transistor, the second transistor, the sixth transistor, the first bias circuit, and the third bias circuit comprise an N-type MOSFET device, and wherein the fifth transistor comprises a P-type MOSFET device.