Apparatus for flexible electronic interfaces and associated methods

• US 9,647,668 B2
• Filed: 01/13/2012
• Issued: 05/09/2017
• Est. Priority Date: 01/13/2012
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ngai, Tony
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US13/350,662
• Publication Number:
  US 20130181257A1
• Time in Patent Office: 1,943 Days
• Field of Search: 257209, 257777
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.

Claims

1. A semiconductor die comprising:

a first flexible interface block, comprising;

at least one interconnect;

at least one buffer coupled to the at least one interconnect;

a routing interface coupled to circuitry integrated in the semiconductor die; and

a controller coupled between the routing interface and the at least one buffer to provide communication between the routing interface and the at least one buffer.

2. The semiconductor die according to claim 1, wherein the first flexible interface block is adapted to provide communication between a first circuit integrated in the semiconductor die and a second circuit external to the semiconductor die.

3. The semiconductor die according to claim 2, wherein the second circuit is adapted to operate according to a protocol, and the controller may be adapted to provide communication to the second circuit using the protocol.

4. The semiconductor die according to claim 2, wherein the first flexible interface block is adapted to provide a customizable interface between the first and second circuits.

5. The semiconductor die according to claim 1, wherein the controller includes hardened logic circuitry.

6. The semiconductor die according to claim 1, wherein the controller includes structured application specific integrated circuit (ASIC) circuitry.

7. The semiconductor die according to claim 1, wherein the controller includes programmable logic circuitry.

8. The semiconductor die according to claim 1, comprising a programmable logic device (PLD), wherein the PLD comprises the first flexible interface block.

9. The semiconductor die according to claim 8, wherein the first flexible interface block is coupled to programmable interconnect of the PLD.

10. The semiconductor die according to claim 9, wherein the programmable interconnect couples to programmable logic.

11. The semiconductor die according to claim 1, further comprising a second flexible interface block, wherein the first and second flexible interface blocks are arranged in a row or in a column.

12. A method of fabricating a semiconductor die, the method comprising:

fabricating a first flexible interface block, comprising;

fabricating at least one interconnect;

fabricating at least one buffer coupled to the at least one interconnect;

fabricating a routing interface coupled to circuitry integrated in the semiconductor die; and

fabricating a controller coupled to provide communication between the routing interface and the at least one buffer, wherein the at least one buffer is external to the routing interface.

13. The method according to claim 12, further comprising fabricating a first circuit in the semiconductor die;

wherein the first flexible interface block is adapted to provide communication between the first circuit and a second circuit external to the semiconductor die.

14. The method according to claim 13, wherein the second circuit is adapted to operate according to a protocol, and the controller may be adapted to provide communication to the second circuit using the protocol.

15. The method according to claim 13, wherein the first flexible interface block is adapted to provide a customizable interface between the first and second circuits.

16. The method according to claim 12, wherein fabricating the controller includes fabricating hardened logic circuitry.

17. The method according to claim 12, wherein fabricating the controller includes fabricating structured application specific integrated circuit (ASIC) circuitry.

18. The method according to claim 12, wherein fabricating the controller includes fabricating programmable logic circuitry.

19. The method according to claim 12, wherein fabricating the first flexible interface block comprises fabricating the first flexible interface block in a programmable logic device (PLD).

20. The method according to claim 19, wherein fabricating the first flexible interface block further comprises coupling the first flexible interface block to programmable interconnect of the PLD.

21. The method according to claim 20, wherein the programmable interconnect couples to programmable logic.

22. The method according to claim 12, further comprising fabricating a second flexible interface block, wherein the first and second flexible interface blocks are arranged in a row or in a column.