Signal receiver

• US 9,647,707 B1
• Filed: 08/12/2016
• Issued: 05/09/2017
• Est. Priority Date: 08/12/2016
• Status: Active Grant

• Current Assignee: Rafael Microelectronics, Inc.
• Original Assignee: Rafael Microelectronics, Inc.
• Inventors: Kan, Meng-Ping
• Primary Examiner(s): Tran, Pablo
• Application Number:
  US15/235,129
• Time in Patent Office: 270 Days
• CPC Class Codes: H04B 1/08 Constructional details, e.g. cabinet
• CPC Class Codes: H04B 1/1036 with automatic suppression of narrow band noise or interference, e.g. by using tuneable notch filters H04B1/123 takes precedence; filter circuits H03H
• CPC Class Codes: H04B 2001/1045 Adjacent-channel interference
• CPC Class Codes: H04B 7/18517 Transmission equipment in earth stations
• CPC Class Codes: H04B 7/18523 Satellite systems for providing broadcast service to terrestrial stations, i.e. broadcast satellite service arrangements specially adapted for satellite broadcast receiving H04H40/90; picture transmission via satellite H04N1/00103; television transmission via satellite H04N7/20

Abstract

A signal receiver includes a first mixer configured to mix its first input with its second input associated with an oscillating output of a first synthesizer into an output; a first splitter configured to split its input associated with the output of the first mixer into a first output and a second output; a first switch matrix configured to switch its first input associated with the first output of the first splitter into a first output; a second switch matrix configured to switch its first input associated with the second output of the first splitter into a first output; a second mixer configured to mix its first input associated with the first output of the first switch matrix with its second input associated with an oscillating output of a second synthesizer into an output; and a third mixer configured to mix its first input associated with the first output of the second switch matrix with its second input associated with an oscillating output of a third synthesizer into an output.

Claims

1. A signal receiver comprising

a first synthesizer configured to generate an oscillating output;

a first mixer configured to mix its first input with its second input associated with said oscillating output of said first synthesizer into an output;

a first splitter configured to split its input associated with said output of said first mixer into a first output and a second output;

a first switch matrix configured to switch its first input associated with said first output of said first splitter into a first output;

a second switch matrix configured to switch its first input associated with said second output of said first splitter into a first output;

a second synthesizer configured to generate an oscillating output;

a second mixer configured to mix its first input associated with said first output of said first switch matrix with its second input associated with said oscillating output of said second synthesizer into an output;

a third synthesizer configured to generate an oscillating output; and

a third mixer configured to mix its first input associated with said first output of said second switch matrix with its second input associated with said oscillating output of said third synthesizer into an output.

2. The signal receiver of claim 1, wherein said first switch matrix, second synthesizer and second mixer are incorporated in a single integrated-circuit (IC) chip, and said second switch matrix, third synthesizer and third mixer are incorporated in another single integrated-circuit (IC) chip.

3. The signal receiver of claim 1 further comprising a fourth mixer configured to mix its first input with its second input associated with said oscillating output of said first synthesizer into an output, a second splitter configured to split its input associated with said output of said fourth mixer into a first output and a second output, wherein said first switch matrix is configured to switch its second input associated with said first output of said second splitter into a second output, wherein said second switch matrix is configured to switch its second input associated with said second output of said second splitter into a second output, a fourth synthesizer configured to generate an oscillating output, a fifth mixer configured to mix its first input associated with said second output of said first switch matrix with its second input associated with said oscillating output of said fourth synthesizer into an output, a fifth synthesizer configured to generate an oscillating output, a sixth mixer configured to mix its first input associated with said second output of said second switch matrix with its second input associated with said oscillating output of said fifth synthesizer into an output, a first combiner configured to combine its first input associated with said output of said second mixer and its second input associated with said output of said fifth mixer into an output and a second combiner configured to combine its first input associated with said output of said third mixer and its second input associated with said output of said sixth mixer into an output.

4. The signal receiver of claim 3, wherein said first switch matrix, second and fourth synthesizers, second and fifth mixers and first combiner are incorporated in a single integrated-circuit (IC) chip, and said second switch matrix, third and fifth synthesizers, third and sixth mixers and second combiner are incorporated in another single integrated-circuit (IC) chip.

5. The signal receiver of claim 3 further comprising a first image rejection filter configured to suppress an image component of its input associated with said output of said second mixer into an output, a second image rejection filter configured to suppress an image component of its input associated with said output of said third mixer into an output, a third image rejection filter configured to suppress an image component of its input associated with said output of said fifth mixer into an output, a fourth image rejection filter configured to suppress an image component of its input associated with said output of said sixth mixer into an output, a sixth synthesizer configured to generate an oscillating output, a seventh mixer configured to mix its first input associated with said output of said first image rejection filter with its second input associated with said oscillating output of said sixth synthesizer into an output, a seventh synthesizer configured to generate an oscillating output, an eighth mixer configured to mix its first input associated with said output of said second image rejection filter with its second input associated with said oscillating output of said seventh synthesizer into an output, an eighth synthesizer configured to generate an oscillating output, a ninth mixer configured to mix its first input associated with said output of said third image rejection filter with its second input associated with said oscillating output of said eighth synthesizer into an output, a ninth synthesizer configured to generate an oscillating output and a tenth mixer configured to mix its first input associated with said output of said fourth image rejection filter with its second input associated with said oscillating output of said ninth synthesizer into an output, wherein said first input of said first combiner is associated with said output of said seventh mixer and said second input of said first combiner is associated with said output of said ninth mixer, wherein said first input of said second combiner is associated with said output of said eighth mixer and said second input of said second combiner is associated with said output of said tenth mixer.

6. The signal receiver of claim 5, wherein said first switch matrix, second, fourth, sixth and eighth synthesizers and second, fifth, seventh and ninth mixers and first combiner are incorporated in a single integrated-circuit (IC) chip, and said second switch matrix, third, fifth, seventh and ninth synthesizers, third, sixth, eighth and tenth mixers and second combiner are incorporated in another single integrated-circuit (IC) chip.

7. The signal receiver of claim 1 further comprising a fourth synthesizer configured to generate an oscillating output, a fourth mixer configured to mix its first input with its second input associated with said oscillating output of said fourth synthesizer into an output, a second splitter configured to split its input associated with said output of said fourth mixer into a first output and a second output, wherein said first switch matrix is configured to switch its second input associated with said first output of said second splitter into a second output, wherein said second switch matrix is configured to switch its second input associated with said second output of said second splitter into a second output, a fifth synthesizer configured to generate an oscillating output, a fifth mixer configured to mix its first input associated with said second output of said first switch matrix with its second input associated with said oscillating output of said fifth synthesizer into an output, a sixth synthesizer configured to generate an oscillating output, a sixth mixer configured to mix its first input associated with said second output of said second switch matrix with its second input associated with said oscillating output of said sixth synthesizer into an output, a first combiner configured to combine its first input associated with said output of said second mixer and its second input associated with said output of said fifth mixer into an output and a second combiner configured to combine its first input associated with said output of said third mixer and its second input associated with said output of said sixth mixer into an output.

8. The signal receiver of claim 7, wherein said first switch matrix, second and fifth synthesizers, second and fifth mixers and first combiner are incorporated in a single integrated-circuit (IC) chip, and said second switch matrix, third and sixth synthesizers, third and sixth mixers and second combiner are incorporated in another single integrated-circuit (IC) chip.

9. The signal receiver of claim 7 further comprising a third combiner configured to combine its first input associated with said output of said first combiner and its second input associated with said output of said second combiner into an output.

10. The signal receiver of claim 1 further comprising a first image rejection filter configured to suppress an image component of its input associated with said output of said second mixer into an output, a second image rejection filter configured to suppress an image component of its input associated with said output of said third mixer into an output, a fourth synthesizer configured to generate an oscillating output, a fourth mixer configured to mix its first input associated with said output of said first image rejection filter with its second input associated with said oscillating output of said fourth synthesizer into an output, a fifth synthesizer configured to generate an oscillating output, a fifth mixer configured to mix its first input associated with said output of said second image rejection filter with its second input associated with said oscillating output of said fifth synthesizer into an output, a first combiner configured to combine its first input associated with said output of said second mixer and its second input into an output and a second combiner configured to combine its first input associated with said output of said third mixer and its second input into an output.

11. The signal receiver of claim 10, wherein said first switch matrix, second and fourth synthesizers, second and fourth mixers and first combiner are incorporated in a single integrated-circuit (IC) chip, and said second switch matrix, third and fifth synthesizers, third and fifth mixers and second combiner are incorporated in another single integrated-circuit (IC) chip.

12. The signal receiver of claim 10, wherein said oscillating output of said second synthesizer and said oscillating output of said fourth synthesizer are configured to be adjusted based on information containing said oscillating output of said second synthesizer.

13. The signal receiver of claim 10 further comprising an optimization unit configured to adjust said oscillating output of said second synthesizer with a first frequency and adjust said oscillating output of said fourth synthesizer with a second frequency, wherein said first and second frequencies have substantially the same level in the opposite directions.

14. The signal receiver of claim 1 configured to be set in an outdoor unit to receive a satellite signal reflected by an antenna dish, wherein said first input of said first mixer is associated with said satellite signal.

15. A single integrated-circuit (IC) chip comprising:

a switch matrix configured to switch its first input into a first output and switch its second input into a second output;

a first synthesizer configured to generate an oscillating output;

a first mixer configured to mix its first input associated with said first output of said switch matrix with its second input associated with said oscillating output of said first synthesizer into an output;

a second synthesizer configured to generate an oscillating output;

a second mixer configured to mix its first input associated with said second output of said switch matrix with its second input associated with said oscillating output of said second synthesizer into an output;

a first filter configured to suppress a component of its input associated with said output of said first mixer into an output;

a second filter configured to suppress a component of its input associated with said output of said second mixer into an output;

a third synthesizer configured to generate an oscillating output;

a third mixer configured to mix its first input associated with said output of said first image rejection filter with its second input associated with said oscillating output of said third synthesizer into an output;

a fourth synthesizer configured to generate an oscillating output;

a fourth mixer configured to mix its first input associated with said output of said second image rejection filter with its second input associated with said oscillating output of said fourth synthesizer into an output; and

a combiner configured to combine its first input associated with said output of said third mixer and its second input associated with said output of said fourth mixer into an output.

16. The single integrated-circuit (IC) chip of claim 15 configured to be set in an outdoor unit to receive a satellite signal reflected by an antenna dish.

17. The single integrated-circuit (IC) chip of claim 15 further comprising an optimization unit configured to adjust said oscillating output of said first synthesizer with a first frequency and adjust said oscillating output of said third synthesizer with a second frequency, wherein said first and second frequencies have substantially the same level in the opposite directions.

18. The single integrated-circuit (IC) chip of claim 15 further comprising a first single-ended-to-differential amplifier configured to amplify its single-ended input into a differential output with a phase difference of substantially 180 degrees, a second single-ended-to-differential amplifier configured to amplify its single-ended input into a differential output with a phase difference of substantially 180 degrees, wherein said first input of said switch matrix comprises a differential input associated with said differential output of said first single-ended-to-differential amplifier, wherein said second input of said switch matrix comprises a differential input associated with said differential output of said second single-ended-to-differential amplifier, wherein said first output of said switch matrix comprises a differential output with a phase difference of substantially 180 degrees, wherein said second output of said switch matrix comprises a differential output with a phase difference of substantially 180 degrees, a first differential-to-differential amplifier configured to amplify its differential input associated with said first output of said switch matrix into its differential output and a second differential-to-differential amplifier configured to amplify its differential input associated with said second output of said switch matrix into its differential output, wherein said first input of said first mixer is associated with said differential output of said first differential-to-differential amplifier, wherein said first input of said second mixer is associated with said differential output of said second differential-to-differential amplifier.

19. A signal receiver comprising

a first switch matrix configured to switch its first input into a first output and switch its second input into a second output;

a first synthesizer configured to generate an oscillating output;

a first mixer configured to mix its first input associated with said first output of said first switch matrix with its second input associated with said oscillating output of said first synthesizer into an output;

a second synthesizer configured to generate an oscillating output;

a second mixer configured to mix its first input associated with said second output of said first switch matrix with its second input associated with said oscillating output of said second synthesizer into an output;

a first combiner configured to combine its first input associated with said output of said first mixer and its second input associated with said output of said second mixer into an output;

a second switch matrix configured to switch its first input into a first output and switch its second input into a second output;

a third synthesizer configured to generate an oscillating output;

a third mixer configured to mix its first input associated with said first output of said second switch matrix with its second input associated with said oscillating output of said third synthesizer into an output;

a fourth synthesizer configured to generate an oscillating output;

a fourth mixer configured to mix its first input associated with said second output of said second switch matrix with its second input associated with said oscillating output of said fourth synthesizer into an output;

a second combiner configured to combine its first input associated with said output of said third mixer and its second input associated with said output of said fourth mixer into an output; and

a third combiner configured to combine its first input associated with said output of said first combiner and its second input associated with said output of said second combiner into an output.

20. The signal receiver of claim 19, wherein said first switch matrix, first and second synthesizers and first and second mixers are incorporated in a single integrated-circuit (IC) chip, and said second switch matrix, third and fourth synthesizers and third and fourth mixers are incorporated in another single integrated-circuit (IC) chip.