Systems and methods for controlling an audio signal path using redundant uninterruptable clock

• US 9,648,414 B1
• Filed: 01/31/2014
• Issued: 05/09/2017
• Est. Priority Date: 01/31/2014
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Das, Tejasvi, Allen, Daniel John
• Primary Examiner(s): Goins, Davetta W
• Assistant Examiner(s): Ganmavo, Kuassi
• Application Number:
  US14/169,946
• Time in Patent Office: 1,194 Days
• Field of Search: 381 74, 381 97- 98, 700 94, 330207 A, 330251, 327171-176, 327 31, 327 33, 327 35, 327 94, 327291, 327298
• CPC Class Codes: G06F 1/00 Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 architectures of general purpose stored program computers G06F15/76
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G11B 20/10527 Audio or video recording; Data buffering arrangements G11B20/12 - G11B20/18 take precedence
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: H03G 3/00 Gain control in amplifiers or frequency changers
• CPC Class Codes: H03G 3/348 Muting in response to a mechanical action or to power supply variations, e.g. during tuning; Click removal circuits
• CPC Class Codes: H03K 3/00 Circuits for generating electric pulses; Monostable, bistable or multistable circuits H03K4/00 takes precedence; for digital function generators in computers G06F1/02
• CPC Class Codes: H04M 3/002 Applications of echo suppressors or cancellers in telephonic connections in two-way loud-speaking telephone systems H04M9/08, echo suppressors or cancellers per se H04B3/20
• CPC Class Codes: H04R 1/403 loud-speakers
• CPC Class Codes: H04R 1/406 microphones
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Responsive to the absence of a reference clock input signal to a clock conditioning circuit for generating a desired clock signal for synchronizing components of an audio signal path, a controller may cause the signal path to receive at the clock input a substitute clock signal in the absence of the reference clock input signal and may modify one or more parameters of the signal path in order to perform one or more of the following: (i) reduce the presence of audio artifacts in the output signal caused by the absence of the reference clock input signal; (ii) power down at least one component of the signal path to reduce power consumed by the signal path; (iii) continue to operate the signal path with the substitute clock signal; and (iv) transition the signal path to a mute condition or a zero volume condition.

Claims

1. An apparatus for providing an audio output signal to an audio transducer comprising:

a signal path having an audio input for receiving an audio input signal, an audio output for providing the audio output signal, and a clock input for receiving a clock signal, wherein the signal path is configured to generate the audio output signal based on the input signal and in conformity with one or more parameters of the signal path; and

a controller configured to;

determine a presence or an absence of a reference clock input signal to a clock conditioning circuit for generating the clock signal, wherein the clock conditioning circuit generates a desired clock signal as the clock signal that is based on the reference clock input signal in the presence of the reference clock input signal and generates a substitute clock signal as the clock signal in the absence of the reference clock input signal such that the clock signal is uninterrupted in the absence of the reference clock input signal, and wherein the reference clock input signal is representative of a desired clock frequency for the clock signal;

measure an output frequency of the clock signal in the presence of the reference clock input signal;

implement a digital code generator for generating a digital code based on the output frequency; and

responsive to determining the absence of the reference clock input signal;

generate the substitute clock signal based on the digital code;

cause the signal path to receive at the clock input the substitute clock signal in the absence of the reference clock input signal;

modify the one or more parameters of the signal path in order to perform one or more of the following;

reduce the presence of audio artifacts in the output signal caused by the absence of the reference clock input signal;

power down at least one component of the signal path;

continue to operate the signal path with the substitute clock signal; and

transition the signal path to a mute condition or a zero volume condition; and

implement a calibration circuit configured to, during a calibration of the clock conditioning circuit;

cause the digital code generator to output a plurality of codes such that the clock conditioning circuit outputs a respective clock frequency responsive to each of the plurality of codes;

measure the respective clock frequencies; and

correlate each of the plurality codes to a certain frequency or frequency range based on the measuring.

2. The apparatus of claim 1, wherein the signal path comprises an analog signal portion having an analog input for receiving an analog input signal and further having the audio output, and configured to generate the output signal based on the analog input signal and in conformity with the one or more parameters.

3. The apparatus of claim 2, wherein the one or more parameters comprise an analog gain of the analog signal portion.

4. The apparatus of claim 3, wherein modifying the one or more parameters comprises ramping the analog gain to zero.

5. The apparatus of claim 2, wherein the audio input signal is a digital signal and the signal path further comprises a digital-to-analog conversion portion having a digital input for receiving a digital input signal and an analog output for providing an analog input signal, the digital-to-analog conversion portion configured to convert the digital input signal into the analog input signal in conformity with the one or more parameters.

6. The apparatus of claim 5, wherein the one or more parameters comprise a digital gain of the digital-to-analog conversion portion.

7. The apparatus of claim 6, wherein modifying the one or more parameters comprises ramping the digital gain to zero.

8. The apparatus of claim 1, wherein modifying the one or more parameters comprises modifying the audio input signal.

9. The apparatus of claim 8, wherein modifying the audio input signal comprises ramping the audio input signal to zero.

10. The apparatus of claim 8, wherein modifying the one or more parameters further comprises clamping the analog output to a predetermined direct current voltage.

11. The apparatus of claim 1, wherein modifying the one or more parameters causes the signal path to enter a mode wherein the signal path continues to operate uninterrupted with reduced audio performance of the audio output signal.

12. The apparatus of claim 1, wherein the controller is further configured to, responsive to determining the presence of the input reference signal following the absence of the input reference signal, reinstate the one or more parameters to their respective unmodified settings.

13. The apparatus of claim 1, wherein the clock conditioning circuit comprises a phase-locked loop.

14. The apparatus of claim 13, wherein the apparatus includes the clock conditioning circuit.

15. The apparatus of claim 14, wherein the phase-locked loop is, responsive to the absence of the reference clock input signal, configured to transition from a closed-loop mode to an open-loop mode such that an oscillator of the phase-locked loop for generating the clock signal continues to generate the clock signal without interruption.

16. The apparatus of claim 15, wherein the phase-locked loop is, responsive to determining the presence of the input reference signal following the absence of the input reference signal, configured to enter a closed-loop mode.

17. The apparatus of claim 1, further comprising:

the clock conditioning circuit, wherein the clock conditioning circuit is configured to determine based on a first set of one or more parameters whether the reference clock input signal is present or absent; and

a second clock conditioning circuit configured to generate a second desired clock signal as a second clock signal that is based on the reference clock input signal in the presence of the reference clock input signal and generate a second substitute clock signal as the second clock signal in the absence of the reference clock input signal such that the second clock signal is uninterrupted in the absence of the reference clock input signal, wherein the second clock conditioning circuit is configured to determine based on a second set of one or more parameters whether the reference clock input signal is present or absent; and

further wherein the first set of one or more parameters and the second set of one or more parameters are different.

18. A method comprising:

determining a presence or an absence of a reference clock input signal to a clock conditioning circuit for generating a clock signal, wherein the clock conditioning circuit generates a desired clock signal as the clock signal that is based on the reference clock input signal in the presence of the reference clock input signal and generates a substitute clock signal as the clock signal in the absence of the reference clock input signal such that the clock signal is uninterrupted in the absence of the reference clock input signal, and wherein the reference clock input signal is representative of a desired clock frequency for the clock signal;

measuring an output frequency of the clock signal in the presence of the reference clock input signal;

generating a digital code based on the output frequency; and

responsive to determining the absence of the reference clock input signal;

causing a signal path to receive at a clock input the substitute clock signal in the absence of the reference clock input signal, wherein the signal path comprises an audio input for receiving an audio input signal, an audio output for providing an audio output signal, and the clock input for receiving the clock signal;

generating the substitute clock signal based on the digital code;

modifying one or more parameters of the signal path in order to reduce the presence of audio artifacts in the output signal caused by the absence of the reference clock input signal, in order to perform one or more of the following;

reducing the presence of audio artifacts in the output signal caused by the absence of the reference clock input signal;

powering down at least one component of the signal path;

continuing to operate the signal path with the substitute clock signal; and

transitioning the signal path to a mute condition or a zero volume condition; and

during a calibration of the clock conditioning circuit;

causing the digital code generator to output a plurality of codes such that the clock conditioning circuit outputs a respective clock frequency responsive to each of the plurality of codes;

measuring the respective clock frequencies; and

correlating each of the plurality codes to a certain frequency or frequency range based on the measuring;

wherein the signal path is configured to generate the audio output signal based on the input signal and in conformity with one or more parameters of the signal path.

19. The method of claim 18, wherein the signal path comprises an analog signal portion having an analog input for receiving an analog input signal and further having the audio output, and configured to generate the output signal based on the analog input signal and in conformity with the one or more parameters.

20. The method of claim 19, wherein the one or more parameters comprise an analog gain of the analog signal portion.

21. The method of claim 20, wherein modifying the one or more parameters comprises ramping the analog gain to zero.

22. The method of claim 19, wherein the audio input signal is a digital signal and the signal path further comprises a digital-to-analog conversion portion having a digital input for receiving a digital input signal and an analog output for providing an analog input signal, the digital-to-analog conversion portion configured to convert the digital input signal into the analog input signal in conformity with the one or more parameters.

23. The method of claim 22, wherein the one or more parameters comprise a digital gain of the digital-to-analog conversion portion.

24. The method of claim 23, wherein modifying the one or more parameters comprises ramping the digital gain to zero.

25. The method of claim 18, wherein modifying the one or more parameters comprises modifying the audio input signal.

26. The method of claim 25, wherein modifying the audio input signal comprises ramping the audio input signal to zero.

27. The method of claim 26, wherein modifying the one or more parameters further comprises clamping the analog output to a predetermined direct current voltage.

28. The method of claim 18, wherein modifying the one or more parameters causes the signal path to enter a mode wherein the signal path continues to operate uninterrupted with reduced audio performance of the audio output signal.

29. The method of claim 18, further comprising, responsive to determining the presence of the input reference signal following the absence of the input reference signal, reinstating the one or more parameters to their respective unmodified settings.

30. The method of claim 18, wherein the clock conditioning circuit comprises a phase-locked loop.

31. The method of claim 30, further comprising transitioning the phase-locked loop from a closed-loop mode to an open-loop mode responsive to the absence of the reference clock input signal, such that an oscillator of the phase-locked loop for generating the clock signal continues to generate the clock signal without interruption.

32. The method of claim 31, further comprising transitioning the phase-locked loop to the closed-loop mode responsive to determining the presence of the input reference signal following the absence of the input reference signal.

33. The method of claim 18, wherein determining the presence or the absence of the reference clock input signal to the clock conditioning circuit comprises determining based on a first set of one or more parameters whether the reference clock input signal is present or absent;

and

determining a presence or an absence of the reference clock input signal to a second clock conditioning circuit for generating a second clock signal, wherein the second clock conditioning circuit generates a second desired clock signal as the second clock signal that is based on the reference clock input signal in the presence of the reference clock input signal and generates a second substitute clock signal as the second clock signal in the absence of the reference clock input signal such that the second clock signal is uninterrupted in the absence of the reference clock input signal, and wherein the reference clock input signal is representative of a desired clock frequency for the second clock signal;

wherein the first set of one or more parameters and the second set of one or more parameters are different.