Digital real time clock monitor for a GNSS receiver and single pin signalling for power-on reset and wake-up interrupt
First Claim
1. A portable electronic device having a Global Navigation Satellite System (GNSS) receiver, comprising:
- a GNSS oscillator configured to output a GNSS timing signal for the GNSS receiver;
a Real Time Clock (RTC) oscillator configured to output an RTC timing signal;
a resistance/capacitance (RC) oscillator configured to output a digital pulse signal; and
a digital RTC monitor Integrated Circuit (IC) configured to monitor the RTC oscillator timing signal, the digital RTC Monitor IC comprising;
an RTC input configured to receive the RTC oscillator timing signal;
an RC input configured to receive the RC oscillator digital pulse signal; and
an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles,wherein the GNSS receiver, when re-starting GNSS operations after the GNSS oscillator has been powered down, does not use the RTC timing signal to re-correlate GNSS operations when the RTC reset signal has been asserted.
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Abstract
Methods, systems, and devices for monitoring a Real Time Clock (RTC) oscillator using Digital Signal Processing (DSP), where a resistance/capacitance (RC) oscillator is configured to output a digital pulse signal and a digital RTC Monitor Integrated Circuit (IC) is configured to monitor the RTC oscillator timing signal using the RC oscillator signal. In one aspect, the RTC Monitor IC includes an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles. A single wire input/output for both reset and interrupt signals between circuits is also described.
21 Citations
17 Claims
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1. A portable electronic device having a Global Navigation Satellite System (GNSS) receiver, comprising:
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a GNSS oscillator configured to output a GNSS timing signal for the GNSS receiver; a Real Time Clock (RTC) oscillator configured to output an RTC timing signal; a resistance/capacitance (RC) oscillator configured to output a digital pulse signal; and a digital RTC monitor Integrated Circuit (IC) configured to monitor the RTC oscillator timing signal, the digital RTC Monitor IC comprising; an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles, wherein the GNSS receiver, when re-starting GNSS operations after the GNSS oscillator has been powered down, does not use the RTC timing signal to re-correlate GNSS operations when the RTC reset signal has been asserted. - View Dependent Claims (2, 3, 4)
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5. An oscillator timing monitor, comprising:
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a resistance/capacitance (RC) oscillator configured to output a digital pulse signal; a digital Integrated Circuit (IC) configured to monitor a Real Time Clock (RTC) oscillator, the digital IC comprising; an RTC input configured to receive a timing signal output by the RTC oscillator; an RC oscillator input configured to receive the digital pulse signal from the RC oscillator; an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles or has become otherwise dysfunctional. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12)
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13. An electronic device, comprising:
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a first circuit comprising; a clock input for receiving a first clock signal; a transmitter for generating each of a power-on, reset, and wake-up interrupt signal, wherein each of a power-on, reset, and wake-up interrupt signal are distinguishable by at least a number of cycles of the first clock signal each of the power-on, reset, and wake-up interrupt signal is asserted; and a single pin output for transmitting the each of a power-on, reset, and wake-up interrupt signal to a second circuit; the second circuit comprising; a single pin input for receiving each power-on, reset, and wake-up interrupt signal transmitted by the first circuit; a clock input for receiving a second clock signal, the second clock signal having the same nominal frequency as the first clock signal; and a detector electrically connected to the single pin input and the clock input, the detector configured to detect each of the power-on, reset, and wake-up interrupt signals by at least a number of cycles of the second clock signal the signal is asserted; and a single line electrically connecting the single pin output of the first circuit to the single pin input of the second circuit, the single line operable to carry each of a power-on, reset, and wake-up interrupt signal from the first circuit to the second circuit. - View Dependent Claims (14, 15, 16, 17)
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Specification