Multi-mode voltage regulation with feedback

• US 9,651,961 B2
• Filed: 12/21/2012
• Issued: 05/16/2017
• Est. Priority Date: 12/27/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Muthukaruppan, Ramnarayanan, Agashe, Pradyumna, Kadali, Uday Bhaskar, Madugonda, Jnaneshwar
• Primary Examiner(s): Choudhury, Zahid
• Application Number:
  US14/129,593
• Publication Number:
  US 20140344589A1
• Time in Patent Office: 1,607 Days
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/077 with parallel connected charge pump stages

Abstract

Methods and systems to regulate a voltage with multiple selectable voltage regulator (VR) modes, using multiple corresponding circuits and/or a configurable circuit. The circuit may be configurable for one or more of a power-gate VR mode, a switched-capacitor VR (SCVR) mode, and a linear mode, such as a low drop-out (LDO) VR mode. A feedback controller, such as a proportional-integral-derivative (PID) controller, may configure and/or control a multi-mode VR for a selected VR mode. The feedback controller may select a VR mode based on a reference voltage and voltage ranges associated with the VR modes. The circuit may be configurable as banks of VRs, and the controller may be implemented to transition between VR modes by switching sub-banks between modes until the transition is complete.

Claims

1. An apparatus, comprising:

first and second of voltage regulator circuits, wherein the first and second banks of voltage regulator circuits are operable as respective first and second banks of parallel gates to regulate resistance between a power source and a voltage rail, and as first and second switched-capacitor voltage regulators; and

a controller configured to,

operate the first and second banks of voltage regulator circuits as the respective first and second switched-capacitor voltage regulators when a reference voltage is within a first voltage range,

operate the first bank of voltage regulator circuits as the first bank of parallel gates, including to determine a number of the gates to close, and operate the second bank of voltage regulator circuits as the second switched-capacitor voltage regulator, during a transition period that begins when the reference voltage transitions from the first voltage range to a second voltage range that is higher the first voltage range, and

operate the first and second banks of voltage regulator circuits as the respective first and second banks of parallel gates after the transition period.

2. The apparatus of claim 1, wherein the controller is further configured to:

operate the first bank of voltage regulator circuits as the first bank of parallel gates when a load of the voltage rail is at a maximum load level.

3. The apparatus of claim 1, wherein:

the controller includes a digitally controllable multi-phase oscillator;

the first bank of voltage regulator circuits is operable as multiple banks of switched-capacitor circuits, each to receive a corresponding set of clock phases from the multi-phase oscillator, when the reference voltage is within the first voltage range; and

the controller is further configured to control the multi-phase oscillator based on a digital difference code indicative of a difference between the reference voltage and the first voltage rail, when the reference voltage is within the first voltage range.

4. The apparatus of claim 1, wherein:

the first bank of voltage regulator circuits includes an operational amplifier to control the bank of parallel gates in a low drop-out mode to regulate charge flow between the power source and the voltage rail based on a difference between the reference voltage and the voltage rail; and

the controller is further configured to operate the first bank of voltage regulator circuits in the low drop-out mode when the reference voltage is within a linear range of the bank of parallel gates.

5. The apparatus of claim 1, wherein:

the first bank of voltage regulator circuits is further operable in multiple switched-capacitor voltage regulator modes, each to reduce a voltage of the power source by a respective one of multiple fractions; and

the controller is further configured to operate the first bank of voltage regulator circuits in one of the switched-capacitor voltage regulator modes to regulate the voltage rail as the respective fraction of the voltage of the power source.

6. The apparatus of claim 5, wherein:

the bank of voltage regulator circuits is operable in the multiple switched-capacitor voltage regulator modes to reduce the voltage of the power source by respective fractions of ¾

, ⅔

, and ½

.

7. The apparatus of claim 1, wherein each voltage regulator circuit of the first bank of voltage regulator circuits includes a first transistor, a capacitive feature, and multiple configuration transistors, and wherein the controller is further configured to:

control the configuration transistors to configure the first transistors as the bank of parallel gates when the reference voltage is within the first voltage range; and

control the configuration transistors to configure the first transistors and the capacitive features as the switched-capacitor voltage regulator when the reference voltage is within the first voltage range.

8. The apparatus of claim 1, wherein the controller includes:

a windowed flash analog-to-digital controller to output a digital difference code indicative of a difference between the reference voltage and the voltage rail;

a digital controller to generate a digital control based on the digital difference code and the reference voltage; and

a digitally-controllable multi-phase ring oscillator to generate one or more clock phases based on the digital control when the first bank of voltage regulator circuits is operated as the first switched-capacitor voltage regulator;

wherein the controller is further configured to control the number of the gates to close with the digital code when the first bank of voltage regulator circuits is operated as the first bank of parallel gates.

9. A system, comprising, an integrated circuit die that includes a first on-die multi-mode voltage regulator to regulate a first voltage rail of the integrated circuit die based on a first reference voltage, wherein the first multi-mode voltage regulator includes:

first and second banks of voltage regulator circuits, wherein the first and second banks of voltage regulator circuits are operable as respective first and second banks of parallel gates to regulate resistance between the first voltage rail and a power source of the integrated circuit die, and as respective first and second switched-capacitor voltage regulators; and

a first controller configured to,

operate the first and second banks of voltage regulator circuits as the respective first and second switched-capacitor voltage regulators when the first reference voltage is within a first voltage range;

operate the first bank of voltage regulator circuits as the first bank of parallel gates, including to determine a number of the gates to close, and operate the second bank of voltage regulator circuits as the second switched-capacitor voltage regulator, during a transition period that begins when the reference voltage transitions from the first voltage range to a second voltage range that is higher than the first voltage range, and

operate the first and second banks of voltage regulator circuits as the respective first and second banks of parallel gates at an end of the transition period.

10. The system of claim 9, wherein the integrated circuit die further includes:

a second on-die multi-mode voltage regulator to regulate a second voltage rail of the integrated circuit die based on a second reference voltage; and

a graphics processor;

wherein each of the first and second voltage rails is configured to provide electric power to a respective one or more of a core, a partition, and a memory block of the graphics processor.

11. The system of claim 9 or claim 10, wherein the integrated circuit die further includes a processor, the system further including:

a communication system to interface between the processor and a communication network;

a display to present information from the processor; and

a human interface device (HID) to receive user input.

12. The system of claim 11, wherein the communication system includes a wireless communication system, the system further including:

a mobile hand-held housing to receive the IC die, the communication system, the display, and a battery to provide the power source.

13. A non-transitory computer readable medium encoded with a computer program that includes instructions to cause a controller to:

operate first and second banks of voltage regulator circuits as respective first and second switched-capacitor voltage regulators when a reference voltage is within a first voltage range;

operate the first bank of voltage regulator circuits as a first bank of parallel gates, including to determine a number of the gates to close, to regulate resistance between a power source and a the voltage rail, and operate the second bank of voltage regulator circuits as the second switched-capacitor voltage regulator, when the reference voltage is within a second voltage range that is higher than the first voltage range, and

operate the first bank of voltage regulator circuits as the first bank of parallel gates and operate the second bank of voltage regulator circuits as a second bank of parallel gates, after the transition period switched-capacitor voltage regulator when the reference voltage is within a second voltage range that is below the first voltage range.

14. The non-transitory computer readable medium of claim 13, further including instructions to cause the controller to:

operate the first bank of voltage regulator circuits as the first bank of parallel gates when a load of the voltage rail is at a maximum load level.

15. The non-transitory computer readable medium of claim 13, further including instructions to cause the controller to:

operate the first bank of voltage regulator circuits in a low drop-out mode when the reference voltage is within a linear range of the bank of parallel gates to control the bank of parallel gates with an operational amplifier based on a difference between the reference voltage and the voltage rail to regulate charge flow between the power source and the voltage rail.

16. The non-transitory computer readable medium of claim 13, further including instructions to cause the controller to:

operate the first bank of voltage regulator circuits in one of multiple switched-capacitor voltage regulator modes to regulate the voltage rail as a respective one of multiple fractions of a voltage of the power source, when the reference voltage is within the first voltage range.

17. The non-transitory computer readable medium of claim 16, wherein the multiple switched-capacitor voltage regulator modes include fractional reductions of ¾

, ⅔

, and ½

.