Recovery algorithm in non-volatile memory

• US 9,652,321 B2
• Filed: 09/23/2014
• Issued: 05/16/2017
• Est. Priority Date: 09/23/2014
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Motwani, Ravi H., Pangal, Kiran
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US14/493,956
• Publication Number:
  US 20160085621A1
• Time in Patent Office: 966 Days
• Field of Search: 714764, 714758, 714763, 714768, 714773, 714746, 714718, 714799, 714 62, 714 42, 714 48, 714 54, 711103-105, 365200, 365201, 36518509
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1108 Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping

Abstract

Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.

Claims

1. A memory, comprising:

a memory device; and

a controller coupled to the memory device and comprising logic, at least partially including hardware logic, configured to;

receive a read request from a host device for read data stored in the memory device, wherein a portion of the read data is stored in each of a plurality of dies and a portion of an error correction code (ECC) codeword associated with the read data is stored in each of the plurality of dies;

in response to the read request, retrieve the read data and the ECC codeword from the plurality of dies;

perform an ECC check on the read data retrieved from the plurality of dies; and

invoke a recovery algorithm in response to an error in the ECC check.

2. The memory of claim 1, wherein:

the ECC check comprises evaluating a result of performing an Exclusive OR (XOR) operation on the read data and the ECC codeword.

3. The memory of claim 2, wherein the logic is further configured—

to;

calculate a second XOR from the read data retrieved from the plurality of dies and the result of performing the XOR operation on the read data retrieved from the plurality of dies.

4. The memory of claim 3, wherein the logic is further configured to:

return the read data to the host device when the result of performing the second XOR is all zeroes.

5. The memory of claim 3, wherein the logic is further configured to successively:

locate a position of a 1 in the second XOR; and

implement a loop which traverses the plurality of dies to successively;

flip a bit in a die of the plurality of dies at a position corresponding to the position of the 1 in the second XOR; and

recalculate the second XOR.

6. The memory of claim 5, wherein the logic is further configured to:

return the read data to the host device when the contents of the second XOR are all zeroes.

7. The memory of claim 5, wherein the logic is further configured to:

return a read error to the host device when the contents of the second XOR includes a 1.

8. An electronic device, comprising:

a processor; and

a memory, comprising;

a memory device; and

a controller coupled to the memory device and comprising logic, at least partially including hardware logic, to;

receive a read request from the processor for a line of read data stored in the memory device, wherein the line of read data is spread across a plurality of dies and comprises an error correction code (ECC) codeword spread across the plurality of dies;

retrieve the line of read data and the ECC codeword from the plurality of dies;

perform an ECC check on the line of read data retrieved from the plurality of dies; and

invoke a recovery algorithm in response to an error in the ECC check.

9. The electronic device of claim 8, wherein:

the ECC check comprises evaluating an XOR of the line of read data and the ECC codeword.

10. The electronic device of claim 9, wherein the logic is further configured to:

calculate a second XOR from the line of read data retrieved from the plurality of dies and the XOR of the line of read data retrieved from the plurality of dies.

11. The electronic device of claim 10, wherein the logic is further configured to:

return the line of read data to the processor when the contents of the second XOR are all zeroes.

12. The electronic device of claim 10, wherein the logic is further configured to successively:

locate a position of a 1 in the second XOR; and

implement a loop which traverses the plurality of dies to successively;

flip a bit in a die of the plurality of dies at a position corresponding to the position of the 1 in the second XOR; and

recalculate the second XOR.

13. The electronic device of claim 12, wherein the logic is further configured to:

return the line of read data to the processor when the contents of the second XOR are all zeroes.

14. The electronic device of claim 12, wherein the logic is further configured to:

return a read error to the processor when the contents of the second XOR includes a 1.

15. A computer program product comprising logic instructions stored on a nontransitory computer readable medium which, when executed by a controller coupled to a memory device, configure the controller to:

receive a read request from a host device for a line of read data stored in the memory device, wherein the line of read data is spread across a plurality of dies and comprises an error correction code (ECC) codeword spread across the plurality of dies;

retrieve the line of read data and the ECC codeword from the plurality of dies;

perform an ECC check on the line of read data retrieved from the plurality of dies; and

invoke a recovery algorithm in response to an error in the ECC check.

16. The computer program product of claim 15, wherein:

the ECC check comprises evaluating an XOR of the line of read data and the ECC codeword.

17. The computer program product of claim 16, wherein the logic instructions further configure the controller to:

calculate a second XOR from the line of read data retrieved from the plurality of dies and the XOR of the line of read data retrieved from the plurality of dies.

18. The computer program product of claim 17, wherein the logic instructions further configure the controller to:

return the line of read data to the host device when the contents of the second XOR are all zeroes.

19. The computer program product of claim 17, wherein the logic instructions further configure the controller to successively:

locate a position of a 1 in the second XOR; and

implement a loop which traverses the plurality of dies to successively;

flip a bit in a die of the plurality of dies at a position corresponding to the position of the 1 in the second XOR; and

recalculate the second XOR.

20. The computer program product of claim 19, wherein the logic instructions further configure the controller to:

return the line of read data to the host device when the contents of the second XOR are all zeroes.

21. The computer program product of claim 19, wherein the logic instructions further configure the controller to:

return a read error to the host device when the contents of the second XOR includes a 1.