Compression of hardware cache coherent addresses

• US 9,652,391 B2
• Filed: 12/30/2015
• Issued: 05/16/2017
• Est. Priority Date: 12/30/2014
• Status: Active Grant

• Current Assignee: Arteris Incorporated
• Original Assignee: Arteris Incorporated
• Inventors: Kruckemyer, David A., Forrest, Craig Stephen
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): LI, HEWY H
• Application Number:
  US14/985,354
• Publication Number:
  US 20160188473A1
• Time in Patent Office: 503 Days
• Field of Search: None
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

Compression of address bits within a cache coherent subsystem of a chip is performed, enabling a cache coherent subsystem to avoid transmitting, storing, and operating upon unnecessary address information. Compression is performed according to any appropriate lossless algorithm, such as discarding of bits or code book lookup. The algorithm may be chosen according to constraints on logic delay and silicon area. An algorithm for minimum area would use a number of bits equal to the rounded up binary logarithm of the sum of all addresses of all memory regions. A configuration tool generates a logic description of the compression algorithm. The algorithm may be chosen automatically by the configuration tool. Decompression may be performed on addresses exiting the coherent subsystem.

Claims

1. A cache coherent subsystem of a System-on-Chip (SoC), the SoC associated with a system address space representing all memory locations addressable by the SoC, each system address within the system address space consisting of a first number of address bits representing the entire system address space, the cache coherent subsystem associated with a plurality of predefined coherent-capable memory regions distributed within the system address space, each of the coherent-capable memory regions corresponding to a memory, the subsystem comprising:

at least one agent that produces a system address within the system address space;

at least one address compression unit comprising hardware logic, the address compression unit configured to accept the system address from the at least one agent; and

the hardware logic configured to map each system address within the plurality of coherent-capable memory regions into a smaller address space that exclusively represents all addresses of the plurality of coherent-capable memory regions,

the address compression unit configured to use the hardware logic to;

determine whether the system address is within a memory region of the plurality of coherent-capable memory regions;

in response to determining the system address is within a memory region of the plurality of coherent-capable memory regions, produce a compressed address represented by a second number of address bits, the compressed address consisting of fewer bits than an original system address, and

using the compressed address to access the memory region of the plurality of coherent-capable memory regions.

2. The cache coherent subsystem of claim 1 further comprising at least one structure for storing addresses, the stored addresses including the compressed address.

3. The cache coherent subsystem of claim 1 further comprising at least one structure for transporting addresses, the transported addresses including the compressed address.

4. The cache coherent subsystem of claim 1 further comprising at least one address decompression unit that accepts the compressed address and produces a decompressed address including the original address.

5. A method of creating a hardware logic for compression of a plurality of coherent-capable memory regions distributed through an entire system address space into a packed address space exclusively representing the plurality of coherent-capable memory regions, the method comprising:

accepting a specification of a plurality of memory regions;

accepting an identification of which of the memory regions are coherent;

configuring hardware logic that compresses each address within the plurality of the coherent-capable memory regions into the packed address space that is a smaller address space than the entire system address space using the specification and the identification; and

outputting a description of the hardware logic, wherein the hardware logic is configured to;

in response to receiving a system address of the entire system address space, determine whether the system address is within a memory region of the plurality of coherent-capable memory regions;

in response to determining the system address is within a memory region of the plurality of coherent-capable memory regions, produce a compressed address represented by a second number of address bits, the compressed address consisting of fewer bits than an original system address.

6. The method of claim 5 further comprising selecting at least one compression algorithm from a plurality of compression algorithms.

7. The method of claim 6, wherein the at least one compression algorithm is pre-selected.

8. The method of claim 6 wherein the compression algorithm is selected from a plurality of available compression algorithms by configuration inputs into the hardware logic.

9. A cache coherent subsystem of a System-on-Chip (SoC), the SoC associated with a system address space representing all memory locations addressable by the SoC, each system address within the system address space consisting of a first number of address bits representing the entire system address space, the cache coherent subsystem associated with at least one predefined coherent-capable memory region distributed within the system address space, the coherent-capable memory region corresponding to a memory, the subsystem comprising:

at least one agent that produces a system address within the system address space;

at least one address compression unit comprising hardware logic, the address compression unit configured to accept the system address from the at least one agent; and

the hardware logic configured to map each system address within the coherent-capable memory region into a smaller address space that exclusively represents all addresses of the coherent-capable memory region,

the address compression unit configured to use the hardware logic to;

determine whether the system address is within the coherent-capable memory region;

in response to determining the system address is within the coherent-capable memory region, produce a compressed address represented by a second number of address bits, the compressed address consisting of fewer bits than an original system address, and

using the compressed address to access the coherent-capable memory region.

10. The cache coherent subsystem of claim 9 further comprising at least one structure for storing addresses, the stored addresses including the compressed address.

11. The cache coherent subsystem of claim 9 further comprising at least one structure for transporting addresses, the transported addresses including the compressed address.

12. The cache coherent subsystem of claim 9 further comprising at least one address decompression unit that accepts the compressed address and produces a decompressed address including the original address.

13. A method of creating a hardware logic for compression of at least one coherent-capable memory region in an entire system address space into a packed address space exclusively representing the coherent-capable memory region, the method comprising:

accepting a specification of a plurality of memory regions;

accepting an identification of at least one memory region that is the coherent-capable memory region;

configuring hardware logic that compresses each address within the coherent-capable memory region into the packed address space that is a smaller address space than the entire system address space using the specification and the identification; and

outputting a description of the hardware logic, wherein the hardware logic is configured to;

in response to receiving a system address of the entire system address space, determine whether the system address is within the coherent-capable memory region;

in response to determining the system address is within the coherent-capable memory region, produce a compressed address represented by a second number of address bits, the compressed address consisting of fewer bits than an original system address.

14. The method of claim 13 further comprising selecting at least one compression algorithm from a plurality of compression algorithms.

15. The method of claim 14, wherein the at least one compression algorithm is pre-selected.

16. The method of claim 14 wherein the compression algorithm is selected from a plurality of available compression algorithms by configuration inputs into the hardware logic.