Secure processor and a program for a secure processor

• US 9,652,635 B2
• Filed: 11/27/2013
• Issued: 05/16/2017
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: Kamada, Jun, Goto, Seiji, Tamiya, Taiji
• Primary Examiner(s): RAHIM, MONJUR
• Application Number:
  US14/091,475
• Publication Number:
  US 20140089676A1
• Time in Patent Office: 1,266 Days
• Field of Search: 713189
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/53 by executing in a restricted environment, e.g. sandbox or secure virtual machine
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/70 Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency

Abstract

The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Claims

1. A method of controlling an integrated circuit including a processor, a non-rewritable memory and a security resource, the method comprising:

executing, by the processor, a first program included in the non-rewritable memory after power-on of the integrated circuit;

authenticating a second program on the basis of a first key included in the security resource by executing the first program;

executing, by the processor, the authenticated second program to issue a request for an access to the security resource to a third program which monitors the request; and

accessing the security resource by the third program,

wherein the third program causes the processor to restrict an access to the security resource by a non-authenticated program and the security resource includes an encryption processing block and an authentication processing block.

2. The method according to claim 1,

wherein the non-rewritable memory is a read only memory.

3. The method according to claim 1,

wherein the second program is stored in a secondary storage.

4. The method according to claim 1,

wherein the third program executes a key process.

5. The method according to claim 4,

wherein the key process includes a key table operation.

6. A method of controlling an integrated circuit including a processor, a non-rewritable memory and a security resource, comprising:

executing, by the processor, a first program included in the non-rewritable memory after power-on of the integrated circuit;

authenticating a second program on the basis of a first key included in the security resource by executing the first program;

executing the authenticated second program to issue a request to a processing monitor; and

accessing the security resource by the processing monitor in response to the issued request,

wherein the processing monitor is configured to restrict an access to the security resource by a non-authenticated program and the security resource includes an encryption processing block and an authentication processing block.

7. The method according to claim 6,

wherein the non-rewritable memory is a read only memory.

8. The method according to claim 6,

wherein the second program is stored in a secondary storage.

9. The method according to claim 6,

wherein the processing monitor executes a key process.

10. The method according to claim 9,

wherein the key process includes a key table operation.

11. The method according to claim 6,

wherein at least a portion of the processing monitor is implemented as a micro code.

12. The method according to claim 6,

wherein at least a portion of the processing monitor is implemented as a wired logic.

13. An integrated circuit comprising:

a security resource including a first key, an encryption processing block and an authentication processing block;

a memory configured to store a first program in a non-rewritable format; and

a processor configured to execute the first program after power-on of the integrated circuit,

wherein the first program causes the processor to perform a first process including;

authenticating a second program on the basis of the first key, and

executing the authenticated second program,

wherein the second program causes the processor to perform a second process including;

issuing a request to a third program which monitors an access to the security resource, and

wherein the third program causes the processor to perform a third process including;

accessing the security resource,

wherein the third program causes the processor to restrict an access to the security resource by a non-authenticated program.

14. The integrated circuit according to claim 13,

wherein the memory is a read only memory.

15. The integrated circuit according to claim 13,

wherein the second program is stored in a secondary storage.

16. The integrated circuit according to claim 13,

wherein the third program executes a key process.

17. The integrated circuit according to claim 16,

wherein the key process includes a key table operation.

18. An integrated circuit comprising:

a security resource including a first key, an encryption processing block and an authentication processing block;

a memory configured to store a first program in a non-rewritable format;

an executing unit configured to execute the first program after power-on of the integrated circuit;

an authenticating unit configured to authenticate a second program on the basis of the first key by executing the first program; and

a processing monitor configured to access the security resource in response to a request issued by execution of the second program,

wherein the processing monitor is configured to restrict an access to the security resource by a non-authenticated program.

19. The integrated circuit according to claim 18,

wherein the memory is a read only memory.

20. The integrated circuit according to claim 18,

wherein the second program is stored in a secondary storage.

21. The integrated circuit according to claim 18,

wherein the processing monitor executes a key process.

22. The integrated circuit according to claim 21,

wherein the key process includes a key table operation.

23. The integrated circuit according to claim 18,

wherein at least a portion of the processing monitor is implemented as a micro code.

24. The integrated circuit according to claim 18,

wherein at least a portion of the processing monitor is implemented as a wired logic.