Complementary bipolar SRAM
First Claim
1. A method of operating a memory cell, the memory cell comprising:
- a first set of lateral bipolar transistors fabricated on a semiconductor substrate, the first set of lateral bipolar transistors forming a first inverter device, and a second set of lateral bipolar transistors fabricated on the semiconductor substrate, the second set of lateral bipolar transistors forming a second inverter device, the first inverter device and second inverter device in a cross-coupled configuration to store a logic state;
a first bipolar transistor of each said first set and second set being an PNP type bipolar transistor having a base terminal, an emitter terminal and a collector terminal, and a second bipolar transistor of each said first set and second set being a NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal,a first conductor electrically coupling an emitter terminal of said PNP type transistor of said first inverter device and said emitter terminal of said PNP type transistor of said second inverter device, said first conductor adapted to receive a first applied voltage; and
a second conductor electrically coupling the first emitter terminal of said NPN transistor of said first inverter device and the first emitter terminal of said NPN transistor of said second inverter device, said second conductor adapted to receive a second applied voltage,wherein said second emitter terminal of said NPN bipolar transistor of said first inverter device is electrically coupled to a bit line true conductor (BLT) for controlling electrical impedance from the first inverter to said BLT conductor, and said second emitter terminal of said NPN bipolar transistor of said second inverter device is electrically coupled to a bit line complement conductor (BLC) for controlling electrical impedance from the second inverter device to said BLC conductor, each said BLT and BLC conductors used to access said stored logic state, wherein said method comprises;
applying a first voltage to said first conductor;
applying a second voltage to said second conductor, wherein one NPN type transistor of either said first inverter device or second inverter device becomes activated responsive to application of said first voltage and second voltage such that electrical current flows through said first emitter terminal of said activated NPN transistor device to said second conductor, andapplying a further voltage to each said respective said BLT conductor and BLC conductor to write a logic state value to or read a logic state value from said memory cell.
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Accused Products
Abstract
A complementary lateral bipolar SRAM device and method of operating. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.
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Citations
9 Claims
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1. A method of operating a memory cell, the memory cell comprising:
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a first set of lateral bipolar transistors fabricated on a semiconductor substrate, the first set of lateral bipolar transistors forming a first inverter device, and a second set of lateral bipolar transistors fabricated on the semiconductor substrate, the second set of lateral bipolar transistors forming a second inverter device, the first inverter device and second inverter device in a cross-coupled configuration to store a logic state; a first bipolar transistor of each said first set and second set being an PNP type bipolar transistor having a base terminal, an emitter terminal and a collector terminal, and a second bipolar transistor of each said first set and second set being a NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal, a first conductor electrically coupling an emitter terminal of said PNP type transistor of said first inverter device and said emitter terminal of said PNP type transistor of said second inverter device, said first conductor adapted to receive a first applied voltage; and a second conductor electrically coupling the first emitter terminal of said NPN transistor of said first inverter device and the first emitter terminal of said NPN transistor of said second inverter device, said second conductor adapted to receive a second applied voltage, wherein said second emitter terminal of said NPN bipolar transistor of said first inverter device is electrically coupled to a bit line true conductor (BLT) for controlling electrical impedance from the first inverter to said BLT conductor, and said second emitter terminal of said NPN bipolar transistor of said second inverter device is electrically coupled to a bit line complement conductor (BLC) for controlling electrical impedance from the second inverter device to said BLC conductor, each said BLT and BLC conductors used to access said stored logic state, wherein said method comprises; applying a first voltage to said first conductor; applying a second voltage to said second conductor, wherein one NPN type transistor of either said first inverter device or second inverter device becomes activated responsive to application of said first voltage and second voltage such that electrical current flows through said first emitter terminal of said activated NPN transistor device to said second conductor, and applying a further voltage to each said respective said BLT conductor and BLC conductor to write a logic state value to or read a logic state value from said memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification