Write abort detection for multi-state memories

• US 9,653,154 B2
• Filed: 09/21/2015
• Issued: 05/16/2017
• Est. Priority Date: 09/21/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Dutta, Deepanshu, Hsu, Cynthia Hua-Ling, Lee, Aaron, Manohar, Abhijeet
• Primary Examiner(s): HOANG, TRI M
• Application Number:
  US14/860,086
• Publication Number:
  US 20170084328A1
• Time in Patent Office: 603 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state'"'"'s read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Claims

1. A method of operating a non-volatile memory circuit, comprising:

initiating a programming operation on a first block of the non-volatile memory circuit, the non-volatile memory circuit having a plurality of blocks formed according to a NAND type architecture in which memory cells of a block are formed along a plurality of word lines, wherein the memory cells store data in an N-bit per cell, multi-state format in which each word line stores N pages of data, where N is greater than or equal to two, and where the word lines of a block are sequentially written in a write sequence from a first end of the block to a second end thereof with each of the word lines being written from an erased state with N pages of data;

aborting the programming operation prior to completion;

subsequently performing a determination of a degree to which the first block was written during the programming operation prior to aborting, including;

searching the first block to determine the first word line in the write sequence that is in the erased state;

subsequently performing, for the word line in the write sequence preceding the determined first word line to be in the erased state, a first read operation to determine whether the preceding word line is readable for the most programmed of the multi-states;

in response to the first read operation determining that the preceding word line is not readable for the most programmed of the multi-states, performing for the preceding word line a second read operation for the least programmed of the multi-states above the erased state; and

based on the second read operation, determining whether programming began on the next word line in the write sequence when the programming operation was aborted.

2. The method of claim 1, wherein the programming operation is aborted in response to an unexpected power down.

3. The method of claim 1, wherein the determination is performed in response to a power up.

4. The method of claim 3, wherein the non-volatile memory circuit is part of a memory system including a controller and the determination is performed by the controller.

5. The method of claim 1, wherein the first read operation is performed with read conditions shifted from a standard read condition for the most programmed of the multi-states.

6. The method of claim 1, wherein the searching the first block to determine the first word line in the write sequence that is in the erased state is performed with a binary search.

7. The method of claim 1, wherein the preceding word line is readable for the most programmed of the multi-states is determined based on error correction code.

8. The method of claim 1, wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium, wherein the word lines run in a horizontal direction relative to the substrate.

9. The method of claim 1, wherein the write sequence includes writing each word line in the write sequence from an erased state to an intermediate program operation with M pages of data and subsequently a further program operation with (N−

M) pages of data, where M is less than N, the determination of the degree to which the first block was written during the programming operation prior to aborting further comprising;

in response to the first read operation determining that the preceding word line is not readable for the most programmed of the multi-states, performing an additional read operation to determine whether the intermediate program operation completed,

wherein the second read operation is further in response to determining that the intermediate program operation did not complete.

10. The method of claim 9, wherein M is two, N is four and the further program operation resolves each state of the intermediate program operation into four states.

11. A method of operating a non-volatile memory circuit, comprising:

initiating a programming operation on a first block of the non-volatile memory circuit, the non-volatile memory circuit having a plurality of blocks formed according to a NAND type architecture in which memory cells of a block are formed along a plurality of word lines, wherein the memory cells store data in an N-bit per cell, multi-state format in which each word line stores N pages of data, where N is greater than or equal to two, and where the word lines of a block are sequentially written in a write sequence from a first end of the block to a second end thereof in a first pass in which each of the word lines being written from an erased state with M pages of data, where M is less than N, and are subsequently written from the first end of the block to the second end thereof in a second pass, in which with each of the word lines are further written with (N−

M) pages of data;

aborting the programming operation prior to completion;

subsequently performing a determination of a degree to which first block was written during the programming operation prior to aborting, including;

determining whether the first pass has completed by performing one or more read operations for the most programmed state of the first pass;

in response to determining that the first pass has completed, searching the first block to determine the last word line in the write sequence for the second pass that is readable for the most programmed of the multi-states;

subsequently performing, for the next word line in the write sequence after the determined last word line, a read operation for the least programmed of the multi-states above the erased state; and

based on the read operation, determining whether programming began on the next word line in the write sequence when the programming operation was aborted.

12. The method of claim 11, wherein determining whether the first pass has completed includes performing a read operation to determine whether the last word line of the write sequence is readable for the most programmed state of the first pass.

13. The method of claim 11, wherein determining whether the first pass has completed includes performing a binary search to determine the last page written in the first pass.

14. The method of claim 13, further comprising:

in response to determining that the first pass has not completed, determining whether the last page written in the first pass completed programming.

15. The method of claim 11, wherein M is two, N is four and the second pass resolves each state of the first pass into four states.

16. The method of claim 11, wherein the programming operation is aborted in response to a power down.

17. The method of claim 11, wherein the determination is performed in response to a power up.

18. The method of claim 17, wherein the non-volatile memory circuit is part of a memory system including a controller and the determination is performed by the controller.

19. The method of claim 11, wherein the searching the first block to determine the last word line in the write sequence for the second pass that is readable for the most programmed of the multi-states is performed with read conditions shifted from a standard read condition for the most programmed of the multi-states.

20. The method of claim 11, wherein the searching the first block to determine the last word line in the write sequence for the second pass that is readable for the most programmed of the multi-states is performed by determining the last read line in the write sequence that is readable for the most programmed of the multi-states is determined based on error correction code.

21. The method of claim 11, wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium, wherein the word lines run in a horizontal direction relative to the substrate.