Partial page memory operations
First Claim
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1. An apparatus comprising:
- a plurality of strings of memory cells, the memory cells formed in a plurality of tiers, the strings of memory cells arrange in memory blocks, wherein a memory block among the memory block includes a first partial block and a second partial block, the first partial block including first memory cells in a first tier of the plurality of tiers, the second partial block including second memory cells in the first tier of the plurality of tiers;
global access lines, each of the global access lines shared by memory cells in a respective tier of the plurality of tiers;
a first local access line shared by the first memory cells, the first local access line coupled to a global access line of the global access lines through a first string driver; and
a second local access line shared by the second memory cells, the second local access line coupled to the global access line through a second string driver.
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Abstract
Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.
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Citations
20 Claims
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1. An apparatus comprising:
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a plurality of strings of memory cells, the memory cells formed in a plurality of tiers, the strings of memory cells arrange in memory blocks, wherein a memory block among the memory block includes a first partial block and a second partial block, the first partial block including first memory cells in a first tier of the plurality of tiers, the second partial block including second memory cells in the first tier of the plurality of tiers; global access lines, each of the global access lines shared by memory cells in a respective tier of the plurality of tiers; a first local access line shared by the first memory cells, the first local access line coupled to a global access line of the global access lines through a first string driver; and a second local access line shared by the second memory cells, the second local access line coupled to the global access line through a second string driver. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus comprising:
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a plurality of strings of memory cells, the memory cells formed in a plurality of tiers, the strings of memory cells arrange in memory blocks, wherein a memory block among the memory block includes a first partial block and a second partial block, the first partial block including first strings of memory cells of the plurality of strings of memory cells, the first strings of memory cells including first memory cells in a first tier of the plurality of tiers, the first memory cells mapped to a first partial page of a page, the second partial block including second strings of memory cells of the plurality of strings of memory cells, the second strings of memory cells including second memory cells in the first tier of the plurality of tiers, the second memory cells mapped to a second partial page of the page; first data lines coupled to the first strings of memory cells; and second data lines different from the first data lines, the second data lines coupled to the second strings of memory cells. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method comprising:
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receiving first data; storing the first data in a first partial page of a memory device; and receiving second data; storing the second data in a second partial page of the page after the first data is stored in the first partial page, the memory device including; a plurality of strings of memory cells, the memory cells formed in a plurality of tiers, the strings of memory cells arrange in memory blocks, wherein a memory block among the memory block includes a first partial block and a second partial block, the first partial block including first strings of memory cells of the plurality of strings of memory cells, the first strings of memory cells including first memory cells in a first tier of the plurality of tiers, the second partial block including second strings of memory cells of the plurality of strings of memory cells, the second strings of memory cells including second memory cells in the first tier of the plurality of tiers; first data lines coupled to the first strings of memory cells, the first partial page mapped to the first memory cells; and second data lines coupled to the second strings o memory cells, second data lines being different from the first data lines, the second partial page mapped to the second memory cells. - View Dependent Claims (17, 18, 19, 20)
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Specification