Storage device and operating method thereof

• US 9,653,172 B2
• Filed: 02/23/2016
• Issued: 05/16/2017
• Est. Priority Date: 09/17/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Hee Youl
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US15/050,946
• Publication Number:
  US 20170084340A1
• Time in Patent Office: 448 Days
• Field of Search: 36518511, 36518518
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

There are provided a storage device and an operating method thereof. A storage device includes a main block including a plurality of sub-blocks, a peripheral circuit for generating operation voltages used in a read operation of a selected sub-block among the sub-blocks and performing the read operation of the selected sub-block by using the operation voltages, and a control logic for, when an erased sub-block among the sub-blocks is included in the read operation, controlling the peripheral circuit to perform the read operation by lowering levels of some of the operation voltages.

Claims

1. A storage device comprising:

a memory block including a plurality of sub-blocks having normal cells storing normal data and spare cells storing information on erased sub-blocks;

a peripheral circuit suitable for generating operation voltages used in a read operation on a selected sub-block, and performing the read operation on the selected sub-block using the operation voltages; and

a control logic suitable for, in the read operation, controlling the peripheral circuit to lower a level of at least one operation voltage when an erased sub-block is included in the memory block.

2. The storage device of claim 1, wherein, in the read operation, the peripheral circuit generates:

a first read voltage applied to a selected word line coupled to the memory block or a second read voltage lower than the first read voltage;

a first pass voltage applied to unselected word lines coupled to the memory block or a second pass voltage lower than the first pass voltage; and

a first turn-on voltage applied to select lines coupled to the memory block or a second turn-on voltage lower than the first turn-on voltage.

3. The storage device of claim 2, wherein the memory block includes U-shaped strings including a pipe transistor, and

wherein the peripheral circuit, in the read operation, generates a first pipe voltage applied to a pipe line coupled to a gate of the pipe transistor or a second pipe voltage lower than the first pipe voltage.

4. The storage device of claim 2, wherein, when the erased sub-block is not included in the memory block, the peripheral circuit generates the first read voltage, the first pass voltage, and the first turn-on voltage, and

wherein, when the erased sub-block is included in the memory block, the peripheral circuit generates at least one of the second read voltage, the second pass voltage, and the second turn-on voltage.

5. The storage device of claim 1, wherein the control logic includes a register storing information on erased sub-blocks.

6. The storage device of claim 5, wherein the register stores various read parameters set according to a number of the erased sub-blocks.

7. A method of operating a storage device, the method comprising:

determining whether an erased sub-block exists in a selected memory block; and

performing, when it is determined that the erased sub-block exists, a read operation on the selected memory block using second operation voltages having lower levels than first operation voltages which are applied to the selected memory block when it is determined that the erased sub-block does not exist,

wherein the first operation voltages include a first read voltage applied to a selected word line, a first pass voltage applied to unselected word lines, a first source turn-on voltage applied to a source select line, and a first drain turn-on voltage applied to a drain select line, and

wherein the second operation voltages include at least one of a second source turn-on voltage lower than the first source turn-on voltage, and a second drain turn-on voltage lower than the first drain turn-on voltage.

8. The method of claim 7, wherein the read operation is performed on a programmed sub-block included in the selected memory block.

9. The method of claim 7, wherein the second operation voltages include at least one of a second read voltage lower than the first read voltage, and a second pass voltage lower than the first pass voltage.

10. The method of claim 7, wherein the selected memory block includes U-shaped strings including a pipe transistor, and

wherein a first pipe voltage coupled to a gate of the pipe transistor or a second pipe voltage lower than the first pipe voltage is applied when the read operation is performed.

11. The method of claim 7, wherein, when dummy cells are included in the selected memory block, the first pass voltage or the second pass voltage is applied to dummy lines coupled to gates of the dummy cells when the read operation is performed.

12. A storage device comprising:

a memory block including a plurality of sub-blocks;

a peripheral circuit suitable for generating operation voltages used in a read operation on a selected sub-block, and performing the read operation on the selected sub-block using the operation voltages; and

a control logic suitable for, in the read operation, controlling the peripheral circuit in response to a command and an address to lower a level of at least one operation voltage when an erased sub-block is included in the memory block, wherein the control logic includes a register storing information of the erased sub-block.

13. The storage device of claim 12, wherein, in the read operation, the peripheral circuit generates:

a first read voltage applied to a selected word line coupled to the memory block or a second read voltage lower than the first read voltage;

a first pass voltage applied to unselected word lines coupled to the memory block or a second pass voltage lower than the first pass voltage; and

a first turn-on voltage applied to select lines coupled to the memory block or a second turn-on voltage lower than the first turn-on voltage.

14. The storage device of claim 12, wherein, when the erased sub-block is not included in the memory block, the peripheral circuit generates the first read voltage, the first pass voltage, and the first turn-on voltage, and

wherein, when the erased sub-block is included in the memory block, the peripheral circuit generates at least one of the second read voltage, the second pass voltage, and the second turn-on voltage.