Memory cell with different program and read paths for achieving high endurance

• US 9,653,173 B1
• Filed: 12/04/2016
• Issued: 05/16/2017
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Lo, Chun-Yuan, Chang, Wei-Chen, Wang, Shih-Chen
• Primary Examiner(s): Hidalgo, Fernando
• Application Number:
  US15/368,658
• Time in Patent Office: 163 Days
• Field of Search: 36518505, 36518501, 36518518, 36518526, 36518529, 365 45, 365 51, 365 63, 365149, 365188
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell

Abstract

A memory cell includes a coupling device, a read transistor, a first read selection transistor, a second read selection transistor, an erase device, a program transistor, and a program selection transistor. The coupling device is formed on a first doped region. The erase device is formed on a second doped region. The read transistor, the first read selection transistor, the second read selection transistor, the program transistor, and the program selection transistor are formed on a third doped region. A gate terminal of the coupling device is coupled to a common floating gate. A gate terminal of the erase device is coupled to the floating gate. During a program operation, electrical charges are moved from the common floating gate. During an erase operation, electrical charges are ejected from the common floating gate to the erase device.

Claims

1. A memory cell comprising:

a coupling device comprising;

a first terminal configured to receive a control line signal; and

a second terminal;

a read transistor comprising;

a first terminal;

a control terminal coupled to the second terminal of the coupling device; and

a second terminal;

a first read selection transistor comprising;

a first terminal coupled to the second terminal of the read transistor;

a control terminal configured to receive a word line signal; and

a second terminal configured to receive a bit line signal;

a second read selection transistor comprising;

a first terminal configured to receive a read source line signal;

a control terminal configured to receive a read select gate signal; and

a second terminal coupled to the first terminal of the read transistor;

an erase device comprising;

a first terminal configured to receive an erase line signal; and

a second terminal coupled to the second terminal of the coupling device;

a program transistor comprising;

a first terminal; and

a control terminal coupled to the second terminal of the coupling device; and

a program selection transistor comprising;

a first terminal configured to receive a program source line signal;

a control terminal configured to receive a program select gate signal; and

a second terminal coupled to the first terminal of the program transistor.

2. The memory cell of claim 1, wherein the program transistor further comprises a second terminal kept floated.

3. The memory cell of claim 1, wherein the coupling device is formed on a first doped region and the erase device is formed on a second doped region.

4. The memory cell of claim 1, wherein the read transistor, the first read selection transistor, the second read selection transistor, the program transistor, and the program selection transistor are formed on a third doped region.

5. The memory cell of claim 1, wherein the read transistor and the program transistor are floating gate transistors, the coupling device and the erase device are MOS capacitors.

6. The memory cell of claim 1, the word line signal, the read select gate signal, and the program select gate signal are generated from a common node physically contacted with a polycrystalline silicon layer.

7. The memory cell of claim 1, wherein during a program operation of the memory cell, the first read selection transistor and the second read selection transistor are turned OFF.

8. The memory cell of claim 7, wherein the control line signal is at a first voltage, the read source line signal is at a second voltage, the read select gate signal is at the second voltage, the word line signal is at the second voltage, the bit line signal is at the second voltage, the erase line signal is at the first voltage, the program select gate signal is at the second voltage, the program source line signal is at a ground voltage, the first voltage is greater than the second voltage, and the second voltage is greater than the ground voltage.

9. The memory cell of claim 1, wherein during a program inhibition operation of the memory cell, the program selection transistor is turned OFF.

10. The memory cell of claim 9, wherein the control line signal is at a first voltage, the read source line signal is at a second voltage, the read select gate signal is at the second voltage, the word line signal is at the second voltage, the bit line signal is at the second voltage, the erase line signal is at the first voltage, the program select gate signal is at the second voltage, the program source line signal is at the second voltage, and the first voltage is greater than the second voltage.

11. The memory cell of claim 1, wherein during a read operation when the memory cell is selected, the control line signal is at a sixth voltage, the read source line signal is at the ground voltage, the read select gate signal is at a third voltage, the word line signal is at the third voltage, the bit line signal is at a fourth voltage, the erase line signal is at the sixth voltage, the program select gate signal is at the third voltage, the program source line signal is at the ground voltage, the third voltage and the fourth voltage are greater than the ground voltage, and the sixth voltage is equal to or greater than the ground voltage.

12. The memory cell of claim 1, wherein during a read operation when the memory cell is unselected, the control line signal is at a sixth voltage, the read source line signal is at the ground voltage, the read select gate signal is at a third voltage, the word line signal is at the third voltage, the bit line signal is at a seventh voltage or under a floating state, the erase line signal is at the sixth voltage, the program select gate signal is at the third voltage, the program source line signal is at the ground voltage, the third voltage is greater than the ground voltage, the sixth voltage is equal to or greater than the ground voltage, and the seventh voltage is equal to or in between the third voltage and the ground voltage.

13. The memory cell of claim 1, wherein during an erase operation of the memory cell, the control line signal is at a ground voltage, the read source line signal is at the ground voltage, the read select gate signal is at a second voltage, the word line signal is at the second voltage, the bit line signal is at the ground voltage, the erase line signal is at a fifth voltage, the program select gate signal is at the second voltage, the program source line signal is at the ground voltage, the fifth voltage is greater than the second voltage, and the second voltage is greater than the ground voltage.

14. The memory cell of claim 13, wherein the first read selection transistor, the second read selection transistor, and the program selection transistor are turned ON.

15. The memory cell of claim 1, wherein the second terminal of the coupling device is coupled to a common floating gate.

16. The memory cell of claim 15, wherein during a program operation of the memory cell, the first terminal of the coupling device receives a high voltage, the program selection transistor is turned ON, and electrical charges are ejected from the program transistor to the common floating gate.

17. The memory cell of claim 1, wherein a source/drain junction of the read transistor is coupled to a source/drain junction of the first read selection transistor or the second read selection transistor.

18. The memory cell of claim 1, wherein the second terminal of the erase device is coupled to a common floating gate.

19. The memory cell of claim 18, wherein during an erase operation of the memory cell, the first terminal of the erase device receives a high voltage and electrical charges are ejected from the common floating gate to the erase device.

20. The memory cell of claim 1, wherein a source/drain junction of the program transistor is coupled to a source/drain junction of the program selection transistor.

21. The memory cell of claim 1, wherein the word line signal, the read select gate signal, and the program select gate signal comprise selection information, the control line signal and the erase line signal comprise status control information, and the bit line signal, the read source line signal, and the program source line signal comprise address information.

22. The memory cell of claim 1, wherein a word line carrying the word line signal, a read selection gate line carrying the read select gate signal, a program selection gate line carrying the program select gate signal, a control line carrying the control line signal, an erase line carrying the erase line signal, a read source line carrying the read source line signal are coupled to a plurality of row memory cells to form a page unit of a memory array.

23. The memory cell of claim 22, wherein when the page unit is unselected, the control line signal, the read source line signal, the read select gate signal, the word line signal, the erase line signal, and the program select gate signal are at a ground voltage.

24. The memory cell of claim 22, wherein a plurality of bit lines carrying the bit line signals and a plurality of program source lines carrying the program source line signals are coupled to respective column memory cells of the memory array.

25. The memory cell of claim 1, wherein a bit line carrying the bit line signal and a program source line carrying the program source line signal are coupled to a plurality of column memory cells of a memory array.