Testing method, manufacturing method, and testing device of memory device

• US 9,653,182 B1
• Filed: 09/09/2016
• Issued: 05/16/2017
• Est. Priority Date: 03/01/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Toko, Masaru, Hosotani, Keiji, Kishi, Tatsuya, Aikawa, Hisanori
• Primary Examiner(s): Tran, Michael
• Application Number:
  US15/261,730
• Time in Patent Office: 249 Days
• Field of Search: 365158, 365173
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/06 Acceleration testing
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

According to one embodiment, a testing method of a memory device includes annealing the memory device, the memory device including a memory element; performing, after the annealing, to the memory element a process which sets a first magnetization orientation of a first ferromagnetic layer to be antiparallel to a second magnetization orientation of the second ferromagnetic layer; reading, after the performing of the process, data from the memory element; and determining the memory element as defective due to the second magnetization orientation being parallel to a third magnetization orientation of a third ferromagnetic layer, when data represented by the first magnetization orientation being antiparallel to the second magnetization orientation differs from the read data.

Claims

1. A testing method of a memory device, comprising:

annealing the memory device, the memory device including a memory element, the memory element including a first ferromagnetic layer, a second ferromagnetic layer, a third ferromagnetic layer, a first nonmagnetic layer, and a second nonmagnetic layer, the first nonmagnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer, and the second nonmagnetic layer being disposed between the second ferromagnetic layer and the third ferromagnetic layer;

performing, after the annealing, to the memory element a process which sets a first magnetization orientation of the first ferromagnetic layer to be antiparallel to a second magnetization orientation of the second ferromagnetic layer;

reading, after the performing of the process which sets the first magnetization orientation to be antiparallel to the second magnetization orientation, data from the memory element; and

determining the memory element as defective due to the second magnetization orientation being parallel to a third magnetization orientation of the third ferromagnetic layer, when data represented by the first magnetization orientation being antiparallel to the second magnetization orientation differs from the read data.

2. The method of claim 1, wherein a thermal load on the memory element by the annealing is greater than a thermal load by a reflow soldering.

3. The method of claim 1, wherein the annealing is performed after forming a passivation layer above the memory element, and wherein the annealing, the performing of the process which sets the first magnetization orientation to be antiparallel to the second magnetization orientation, the reading, and the determining are performed before a reflow soldering to the memory device.

4. The method of claim 1, further comprising magnetizing the second magnetization orientation to be antiparallel to the third magnetization orientation,

wherein the annealing includes annealing the memory device including the memory element which was magnetized by the magnetizing.

5. The method of claim 1, wherein the second ferromagnetic layer and the third ferromagnetic layer are antiferromagnetically coupled by the second nonmagnetic layer.

6. The method of claim 1, wherein the annealing, the performing of the process which sets the first magnetization orientation to be antiparallel to the second magnetization orientation, the reading, and the determining are executed on a plurality of the memory elements formed on an identical wafer.

7. A testing device of a memory device, comprising an annealing unit, and a function tester including a writing circuit, a reading circuit and a determining circuit,

wherein the annealing unit is configured to anneal the memory device including a memory element, the memory element including a first ferromagnetic layer, a second ferromagnetic layer, a third ferromagnetic layer, a first nonmagnetic layer, and a second nonmagnetic layer, the first nonmagnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer, and the second nonmagnetic layer being disposed between the second ferromagnetic layer and the third ferromagnetic layer;

the writing circuit is configured to perform, after a process of the annealing, to the memory element a process which sets a first magnetization orientation of the first ferromagnetic layer to be antiparallel to a second magnetization orientation of the second ferromagnetic layer;

the reading circuit is configured to read, after the process of the performing which sets the first magnetization orientation to be antiparallel to the second magnetization orientation, data from the memory element; and

the determining circuit is configured to determine the memory element as defective due to the second magnetization orientation being parallel to a third magnetization orientation of the third ferromagnetic layer, when data represented by the first magnetization orientation being antiparallel to the second magnetization orientation differs from the read data.

8. The device of claim 7, wherein the annealing unit is configured to be capable of executing annealing with a thermal load which is greater than a thermal load by a reflow soldering.

9. The device of claim 7, wherein the annealing unit is configured to anneal the memory device after a passivation layer is formed above the memory element, and wherein the annealing unit, the writing circuit, the reading circuit, and the determining circuit are configured to execute each process before a reflow soldering to the memory device.

10. The device of claim 7, further comprising a magnetic initialization unit configured to magnetize the second magnetization orientation to be antiparallel to the third magnetization orientation,

wherein the annealing unit is configured to anneal the memory device including the memory element which was magnetized by the magnetic initialization unit.

11. The device of claim 7, wherein the annealing unit is configured to anneal the memory element in which the second ferromagnetic layer and the third ferromagnetic layer are antiferromagnetically coupled by the second nonmagnetic layer.

12. The device of claim 7, wherein the annealing unit and the function tester are configured to execute, on a plurality of the memory elements formed on an identical wafer, the process of the annealing, the process of the performing which sets the first magnetization orientation to be antiparallel to the second magnetization orientation, a process of the reading, and a process of the determining.

13. A manufacturing method of a memory device, comprising:

forming a memory element, the memory element including a first ferromagnetic layer, a second ferromagnetic layer, a third ferromagnetic layer, a first nonmagnetic layer, and a second nonmagnetic layer, the first nonmagnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer, and the second nonmagnetic layer being disposed between the second ferromagnetic layer and the third ferromagnetic layer;

annealing the memory device including the formed memory element;

performing, after the annealing, to the memory element a process which sets a first magnetization orientation of the first ferromagnetic layer to be antiparallel to a second magnetization orientation of the second ferromagnetic layer;

reading, after the performing of the process which sets the first magnetization orientation to be antiparallel to the second magnetization orientation, data from the memory element; and

determining the memory element as defective due to the second magnetization orientation being parallel to a third magnetization orientation of the third ferromagnetic layer, when data represented by the first magnetization orientation being antiparallel to the second magnetization orientation differs from the read data.

14. The method of claim 13, wherein a thermal load on the memory element by the annealing is greater than a thermal load by a reflow soldering.

15. The method of claim 13, wherein the producing includes forming a passivation layer above the memory element, and wherein the forming, the annealing, the performing the process which sets the first magnetization orientation to be antiparallel to the second magnetization orientation, the reading, and the determining are performed before a reflow soldering to the memory device.

16. The method of claim 13, further comprising magnetizing the second magnetization orientation to be antiparallel to the third magnetization orientation,

wherein the annealing includes annealing the memory device including the memory element which was magnetized by the magnetizing.

17. The method of claim 13, wherein the second ferromagnetic layer and the third ferromagnetic layer are antiferromagnetically coupled by the second nonmagnetic layer.

18. The method of claim 13, wherein the forming, the annealing, the performing of the process which sets the first magnetization orientation to be antiparallel to the second magnetization orientation, the reading, and the determining are executed on a plurality of the memory elements formed on an identical wafer.

19. The method of claim 13, further comprising avoiding to use the memory element which was determined as defective.