Non-volatile memory module with physical-to-physical address remapping

• US 9,653,184 B2
• Filed: 01/14/2015
• Issued: 05/16/2017
• Est. Priority Date: 06/16/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Frayer, Jack Edward, Mohan, Vidyabhushan
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US14/597,169
• Publication Number:
  US 20150364218A1
• Time in Patent Office: 853 Days
• CPC Class Codes: G06F 11/2094 Redundant storage or storage space G06F11/2056 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/785 with redundancy programming schemes

Abstract

The various embodiments described herein include systems, methods and/or devices used to enable physical-to-physical address remapping in a storage module. In one aspect, the method includes, for each of a sequence of two or more units of non-volatile memory, determining a validity state of a respective unit of memory. In accordance with a determination that the validity state of the respective unit of memory is an invalid state, the method includes storing, in a table, a second address assigned to the respective unit of memory. At least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory. In accordance with a determination that the validity state of the respective unit of memory is a valid state, the method includes forgoing assignment of the second address corresponding to the unit of memory.

Claims

1. A non-volatile memory module, comprising:

a plurality of physical die of non-volatile memory, each physical die having one or more units of memory, each unit of memory being addressable by a respective first address, wherein at least a portion of the respective first address is a physical address portion corresponding to a physical location of the unit of memory;

one or more processors; and

memory storing a set of instructions for execution by the one or more processors, the set of instructions when executed by the one or more processors causing the non-volatile memory module to;

for each unit of memory of a sequence of two or more units of memory in the plurality of physical die of non-volatile memory;

determine a validity state of the unit of memory, wherein the validity state is one of a valid state and an invalid state;

in accordance with a determination that the validity state of the unit of memory is the invalid state;

store, in a table, a second address assigned to the unit of memory, wherein at least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory that is distinct from the unit of memory; and

in accordance with a determination that the validity state of the unit of memory is the valid state;

forgo assignment of the second address corresponding to the unit of memory;

wherein;

the non-volatile memory module is configured to concurrently perform N read/write operations to N physical die, in parallel, where N is an integer greater than 2; and

for each unit of memory determined to be in the invalid state, the second address is an address that preserves the non-volatile memory module'"'"'s ability to concurrently perform N read/write operations to N physical die.

2. The non-volatile memory module of claim 1, wherein:

the table stores entries for each unit of memory in the plurality of physical die; and

for each unit of memory of the sequence of two or more units of memory in the plurality of physical die of non-volatile memory, forgoing assignment of a second address corresponding to the unit of memory includes maintaining, as a default address assignment in the table, the respective first address for the unit of memory.

3. The non-volatile memory module of claim 1, wherein the table is a sparse table storing respective second addresses for only the units of memory that have an invalid state.

4. The non-volatile memory module of claim 1, wherein the instructions, when executed by the one or more processors, further cause the non-volatile memory module to:

receive a read/write command addressed to a respective first address corresponding to a first unit of memory;

access the table;

determine if the table includes a respective second address assigned to the first unit of memory;

in accordance with a determination that the table includes a respective second address assigned to the first unit of memory, direct the read/write command to the respective second address; and

in accordance with a determination that the table does not include a respective second address assigned to the first unit of memory, direct the read/write command to the respective first address.

5. The non-volatile memory module of claim 1, wherein, for a first unit of memory, the validity state is based on as-manufactured characteristics of the first unit of memory.

6. The non-volatile memory module of claim 1, wherein:

each unit of memory comprises a plurality of sub-units of memory; and

determining a validity state of a unit of memory includes determining whether a predefined number of the plurality of sub-units of memory are writable.

7. The non-volatile memory module of claim 1, wherein the instructions, when executed by the one or more processors, further cause the non-volatile memory module to:

for a first unit of memory, in accordance with a determination that the validity state of the first unit of memory is the invalid state;

perform a data recovery operation to recover data written to the first unit of memory; and

write the recovered data to the second unit of memory.

8. The non-volatile memory module of claim 1, wherein the instructions, when executed by the one or more processors, further cause the non-volatile memory module to:

designate one or more units of memory of the plurality of physical die as reserve units of memory; and

assign each second address from among the one or more units of memory designated as reserve units of memory.

9. The non-volatile memory module of claim 1, wherein the instructions, when executed by the one or more processors, further cause the non-volatile memory module to:

determine if one or more remapping criteria are met; and

in accordance with a determination that the one or more remapping criteria are met, trigger performance of the operation of determining a validity state for one or more units of memory of the sequence of two or more units of memory.

10. The non-volatile memory module of claim 8, wherein determining if one or more remapping criteria are met includes determining whether a predefined period of time has elapsed since previously determining a validity state for the one or more units of memory of the sequence of two or more units of memory.

11. The non-volatile memory module of claim 8, wherein determining if one or more remapping criteria are met includes determining whether a bit error rate has exceeded a predefined bit error rate threshold.

12. A method for physical-to-physical address remapping in a non-volatile memory module, comprising:

for each unit of memory of a sequence of two or more units of memory in a plurality of physical die of non-volatile memory;

determining a validity state of the unit of memory, wherein the validity state is one of a valid state and an invalid state;

in accordance with a determination that the validity state of the unit of memory is the invalid state;

storing, in a table, a second address assigned to the unit of memory, wherein at least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory that is distinct from the unit of memory; and

in accordance with a determination that the validity state of the unit of memory is the valid state;

forgoing assignment of the second address corresponding to the unit of memory; and

concurrently performing N read/write operations to N physical die in the non-volatile memory module, in parallel, where N is an integer greater than 2;

wherein, for each unit of memory determined to be in the invalid state, the second address is an address that preserves the non-volatile memory module'"'"'s ability to concurrently perform N read/write operations to N physical die.

13. The method of claim 12, wherein:

the table stores entries for each unit of memory in the plurality of physical die; and

for each unit of memory of the sequence of two or more units of memory in the plurality of physical die of non-volatile memory, forgoing assignment of a second address corresponding to the unit of memory includes maintaining, as a default address assignment in the table, the respective first address for the unit of memory.

14. The method of claim 12, further including:

receiving a read/write command addressed to a respective first address corresponding to a first unit of memory;

accessing the table;

determining if the table includes a respective second address assigned to the first unit of memory;

in accordance with a determination that the table includes a respective second address assigned to the first unit of memory, directing the read/write command to the respective second address; and

in accordance with a determination that the table does not include a respective second address assigned to the first unit of memory, directing the read/write command to the respective first address.

15. The method of claim 12, wherein:

each unit of memory comprises a plurality of sub-units of memory; and

determining a validity state of a unit of memory includes determining whether a predefined number of the plurality of sub-units of memory are writable.

16. The method of claim 12, further including:

for a first unit of memory, in accordance with a determination that the validity state of the first unit of memory is the invalid state;

performing a data recovery operation to recover data written to the first unit of memory; and

writing the recovered data to the second unit of memory.

17. The method of claim 12, further including:

designating one or more units of memory of the plurality of physical die as reserve units of memory; and

assigning each second address from among the one or more units of memory designated as reserve units of memory.

18. The method of claim 12, further including:

determining if one or more remapping criteria are met; and

in accordance with a determination that the one or more remapping criteria are met, triggering performance of the operation of determining a validity state for one or more units of memory of the sequence of two or more units of memory.

19. The method of claim 18, wherein determining if one or more remapping criteria are met includes determining whether a predefined period of time has elapsed since previously determining a validity state for the one or more units of memory of the sequence of two or more units of memory.

20. The method of claim 18, wherein determining if one or more remapping criteria are met includes determining whether a bit error rate has exceeded a predefined bit error rate threshold.

21. A non-transitory computer-readable storage medium, storing one or more programs for execution by one or more processors of a non-volatile memory module, the one or more programs including instructions that cause the non-volatile memory module to:

for each unit of memory of a sequence of two or more units of memory in the plurality of physical die of non-volatile memory;

determine a validity state of the unit of memory, wherein the validity state is one of a valid state and an invalid state;

in accordance with a determination that the validity state of the unit of memory is the invalid state;

store, in a table, a second address assigned to the unit of memory, wherein at least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory that is distinct from the unit of memory; and

in accordance with a determination that the validity state of the unit of memory is the valid state;

forgo assignment of the second address corresponding to the unit of memory; and

concurrently perform N read/write operations to N physical die in the non-volatile memory module, in parallel, where N is an integer greater than 2;

wherein, for each unit of memory determined to be in the invalid state, the second address is an address that preserves the non-volatile memory module'"'"'s ability to concurrently perform N read/write operations to N physical die.

22. The non-transitory computer-readable storage medium of claim 21, wherein the instructions further cause the non-volatile memory module to:

designate one or more units of memory of the plurality of physical die as reserve units of memory; and

assign each second address from among the one or more units of memory designated as reserve units of memory.

23. The non-transitory computer-readable storage medium of claim 21, wherein the instructions further cause the non-volatile memory module to:

determine if one or more remapping criteria are met; and

in accordance with a determination that the one or more remapping criteria are met, trigger performance of the operation of determining a validity state for one or more units of memory of the sequence of two or more units of memory.