Trench having thick dielectric selectively on bottom portion

• US 9,653,342 B2
• Filed: 11/19/2014
• Issued: 05/16/2017
• Est. Priority Date: 11/19/2014
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kawahara, Hideaki, Yang, Hong, Xiong, Yufei, Liu, Yunlong, Kocon, Christopher Boguslaw
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): MOJADDEDI, OMAR F
• Application Number:
  US14/548,029
• Publication Number:
  US 20160141204A1
• Time in Patent Office: 909 Days
• Field of Search: 438244
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/945 Trench capacitors

Abstract

A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor.

Claims

1. A method of fabricating a semiconductor device, comprising:

etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from said top surface into said semiconductor substrate;

forming a dielectric liner comprising a first dielectric material on said bottom surface and said sidewalls of said trench to line said trench;

after forming the dielectric liner, depositing a second dielectric layer comprising a second dielectric material on the dielectric liner to at least partially fill said trench;

partially etching said second dielectric layer to selectively remove said second dielectric layer from an upper portion of said trench while preserving said second dielectric layer on a lower portion of said trench and while preserving the dielectric liner in the upper portion of the trench and the lower portion of the trench, and

filling said trench with a fill material which provides an electrical conductivity that is at least that of a semiconductor, wherein the dielectric liner lines the fill material in the trench.

2. The method of claim 1, wherein a length of said upper portion of said trench is greater than or equal to (≧

) a length of said lower portion of said trench.

3. The method of claim 1, wherein said trench is a field plate associated with a planar gate metal-oxide-semiconductor field-effect transistor (MOSFET), wherein the planar gate is separated from the field plate.

4. The method of claim 1, wherein said trench is a trench gate for a trench gate metal-oxide-semiconductor field-effect transistor (MOSFET).

5. The method of claim 1, wherein said trench is a trench isolation structure for said semiconductor device.

6. The method of claim 1, wherein said trench is a trench capacitor for said semiconductor device.

7. The method of claim 1, wherein said semiconductor substrate comprises an epitaxial layer on a bulk substrate material, and wherein said trench extends into said bulk substrate material.

8. The method of claim 1, wherein said second dielectric material has a k-value≧

5.

9. A method of fabricating a semiconductor device, comprising:

etching a semiconductor substrate to form a trench having sidewalls and a bottom surface;

forming a dielectric liner comprising a first dielectric material on the bottom surface and the sidewalls of the trench to line the trench;

after forming the dielectric liner, depositing a second dielectric layer comprising a second dielectric material on the dielectric liner to at least partially fill the trench;

partially etching the second dielectric layer to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench, wherein the dielectric liner extends along the sidewalls of the trench above a top surface of the second dielectric layer after the partial etching; and

with the dielectric liner extending along the sidewalls of the trench above the top surface of the second dielectric layer, filling the trench with polysilicon, wherein the dielectric liner lines the polysilicon in the trench.

10. The method of claim 9, wherein said trench is a field plate associated with a planar gate metal-oxide-semiconductor field-effect transistor (MOSFET), wherein the planar gate is separated from the field plate.

11. The method of claim 9, wherein said trench is a trench gate for a trench gate metal-oxide-semiconductor field-effect transistor (MOSFET).

12. The method of claim 9, wherein said trench is a trench isolation structure for said semiconductor device.

13. The method of claim 9, wherein said trench is a trench capacitor for said semiconductor device.

14. A method of fabricating a semiconductor device, comprising:

forming a trench filed plate by;

etching a semiconductor substrate to form a trench having sidewalls and a bottom surface;

forming a dielectric liner comprising a first dielectric material on the bottom surface and the sidewalls of the trench to line the trench;

depositing a second dielectric layer comprising a second dielectric material to at least partially fill the trench;

partially etching the second dielectric layer to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench, wherein the dielectric liner extends along the sidewalls of the trench above a top surface of the second dielectric layer after the partial etching; and

with the dielectric liner extending along the sidewalls of the trench above the top surface of the second dielectric layer, filling the trench with polysilicon, wherein the dielectric liner lines the polysilicon in the trench; and

forming a gate electrode on a gate dielectric that is on a top surface of the semiconductor substrate, wherein there is a space between the gate electrode and the polysilicon in the trench.