Semiconductor device and method of manufacturing the same

• US 9,653,400 B2
• Filed: 12/30/2015
• Issued: 05/16/2017
• Est. Priority Date: 01/19/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, Jong-Min, Yim, Tae-Jin, You, Woo-Kyung, Oszinda, Thomas, Jun, Kee-Young, Ahn, Sang-Hoon
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US14/984,085
• Publication Number:
  US 20160211211A1
• Time in Patent Office: 503 Days
• Field of Search: 257750, 257758
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns.

Claims

1. A semiconductor device, comprising:

a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region;

a second interlayer insulating film formed on the first interlayer insulating film in the first region;

a plurality of first conductive patterns formed in the second interlayer insulating film such that they are spaced apart from each other;

at least one second conductive pattern formed in the first interlayer insulating film in the second region; and

air gaps disposed at lateral sides of the plurality of first conductive patterns.

2. The semiconductor device of claim 1,

wherein upper surfaces of the first conductive patterns are coplanar with an upper surface of the second conductive pattern.

3. The semiconductor device of claim 1, further comprising:

a first trench formed in the first interlayer insulating film and filled with the second conductive pattern; and

a sealing film formed on the inner wall of the first trench to seal the inner wall surface of the first interlayer insulating film.

4. The semiconductor device of claim 3, further comprising:

a barrier metal between the sealing film and the second conductive pattern.

5. The semiconductor device of claim 1,

wherein a height of an upper surface of the first interlayer insulating film in the first region is lower than a height of an upper surface of the first interlayer insulating film in the second region.

6. The semiconductor device of claim 1,

wherein each of the first and/or second conductive patterns includes a via penetrating the first interlayer insulating film.

7. The semiconductor device of claim 1, further comprising:

a capping film formed on an upper surface of each of the first and second conductive patterns to cover each of the first and second conductive patterns.

8. The semiconductor device of claim 7,

wherein the capping film includes Co and/or AlN.

9. The semiconductor device of claim 1,

wherein each of the first and second conductive patterns includes Cu, W, Co, and/or Al.

10. The semiconductor device of claim 1,

wherein the air gaps are formed only between the plurality of first conductive patterns.

11. The semiconductor device of claim 1, wherein the second conductive pattern comprises at least two conductive patterns, and

wherein an interval between the at least two second conductive patterns is equal to or greater than an interval between the first conductive patterns.

12. A semiconductor device, comprising:

a first structure including a first region and a second region; and

a second structure including a third region and a fourth region and disposed on the first structure,

wherein the first structure includes;

a first interlayer insulating film including a first porous ultra-low-dielectric constant material;

a second interlayer insulating film formed on the first interlayer insulating film in the first region;

a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other;

at least one second conductive pattern formed in the first interlayer insulating film in the second region; and

first air gaps disposed at lateral sides of the plurality of first conductive patterns, and

wherein the second structure includes;

a third interlayer insulating film containing a second porous ultra-low-dielectric constant material;

a fourth interlayer insulating film formed on the third interlayer insulating film in the third region;

a plurality of third conductive patterns formed in the fourth interlayer insulating film such that the plurality of third conductive patterns are spaced apart from each other;

at least one fourth conductive pattern formed in the third interlayer insulating film in the fourth region; and

second air gaps disposed at lateral sides of the plurality of third conductive patterns.

13. The semiconductor device of claim 12,

wherein the dielectric constant of the first interlayer insulating film is different from the dielectric constant of the third interlayer insulating film.

14. The semiconductor device of claim 13, wherein the dielectric constant of the first interlayer insulating film is greater than the dielectric constant of the third interlayer insulating film.

15. The semiconductor device of claim 12, wherein the porosity of the first porous ultra-low-dielectric constant material is different from the porosity of the second porous ultra-low-dielectric constant material.

16. The semiconductor device of claim 12, further comprising:

a first trench formed in the first interlayer insulating film and filled with the second conductive pattern;

a second trench formed in the third interlayer insulating film and filled with the fourth conductive pattern; and

a sealing film conformally formed on the inner wall of the first trench and/or the second trench to seal the inner wall surface of the first interlayer insulating film and/or the third interlayer insulating film.

17. A semiconductor device, comprising:

a first porous interlayer insulating film containing a porous ultra-low-dielectric constant material;

a plurality of conductive patterns formed on the first interlayer insulating film such that the plurality of conductive patterns are spaced apart from each other;

air gaps formed at lateral sides of the plurality of conductive patterns; and

a second interlayer insulating film formed on the plurality of conductive patterns, the air gaps, and the first interlayer insulating film.

18. The semiconductor device of claim 17,

wherein some of the plurality of conductive patterns include a via pattern penetrating the first interlayer insulating film.

19. The semiconductor device of claim 17,

wherein the porosity of the porous ultra-low-dielectric constant material is 0% to 80%.

20. The semiconductor device of claim 17, further comprising:

a coating film formed between the first interlayer insulating film and the air gaps.