Method of maintaining the state of semiconductor memory having electrically floating body transistor
First Claim
Patent Images
1. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
- a first bipolar device having a first floating base region, a first collector, and a first emitter, anda second bipolar device having a second floating base region, a second collector, and a second emitter,wherein said first floating base region is common to said second floating base region,wherein said first collector is common to said second collector,wherein a state of said memory cell is maintained through a back-bias applied to said first and second collectors, andwherein said first and second collectors are commonly connected to at least two of said memory cells.
4 Assignments
0 Petitions
Accused Products
Abstract
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
291 Citations
20 Claims
-
1. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
-
a first bipolar device having a first floating base region, a first collector, and a first emitter, and a second bipolar device having a second floating base region, a second collector, and a second emitter, wherein said first floating base region is common to said second floating base region, wherein said first collector is common to said second collector, wherein a state of said memory cell is maintained through a back-bias applied to said first and second collectors, and wherein said first and second collectors are commonly connected to at least two of said memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each semiconductor memory cell includes:
-
a first bipolar device having a first floating base region, a first collector, and a first emitter, and a second bipolar device having a second floating base region, a second collector, and a second emitter, wherein said first floating base region is common to said second floating base region, wherein said first collector is common to said second collector, wherein application of back-bias to said collector results in at least two stable floating base region charge levels, and wherein said first and second collectors are commonly connected to at least two of said memory cells. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said plurality of semiconductor memory cells includes:
-
a first bipolar device having a first floating base region, a first collector, and a first emitter; and a second bipolar device having a second floating base region, a second collector, and a second emitter; wherein said first floating base region is common to said second floating base region; wherein said first collector is common to said second collector; and wherein states of said memory cells are maintained upon repeated read operations. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification