Multi-layer interconnected spiral capacitor

• US 9,653,533 B2
• Filed: 02/18/2015
• Issued: 05/16/2017
• Est. Priority Date: 02/18/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhang, Xiaonan, Song, Young Kyu, Jow, Uei-Ming, Lee, Jong-Hoon
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Kilpatrick, Warren H
• Application Number:
  US14/625,484
• Publication Number:
  US 20160240606A1
• Time in Patent Office: 818 Days
• Field of Search: 257534
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/86 having horizontal extensions

Abstract

An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

Claims

1. A multi-layer capacitor, comprising:

a first level planar capacitor, comprising a first level first trace and a first level second trace;

a dielectric layer, arranged over the first level planar capacitor;

a second level planar capacitor, arranged over the dielectric layer, comprising a second level first trace and a second level second trace; and

a bridged-post inter-layer interconnect, comprising

at least two first posts and at least two second posts, extending through the dielectric layer, adjacent to and outside a perimeter of the first level planar capacitor and a perimeter of the second level planar capacitor,

a first level first post coupler and a first level second post coupler, under the dielectric layer, wherein the first level first post coupler is configured to couple the at least two first posts together and to the first level first trace, and the first level second post coupler is configured to couple the first level second trace to at least one of the at least two second posts, and

a second level first post coupler and a second level second post coupler, over the dielectric layer, wherein the second level second post coupler is configured to couple the at least two second posts together and to the second level first trace, and the second level first post coupler is configured to couple the second level first trace to at least one of the at least two first posts.

2. The multi-layer capacitor of claim 1, wherein the first level first trace and the first level second trace are configured to extend adjacent each other, along mutually parallel paths, wherein the mutually parallel paths are in a plane.

3. The multi-layer capacitor of claim 2, wherein the second level first trace is configured in a tracking alignment above the first level first trace, to form a first parallel plate capacitor, and wherein the second level second trace is configured in a tracking alignment above the first level second trace, to form a second parallel plate capacitor.

4. The multi-layer capacitor of claim 1, wherein the first level planar capacitor is a first level spiral capacitor, and the second level planar capacitor is a second level spiral capacitor,

wherein the first level first trace comprises a first level first spiral winding, the first level second trace comprises a first level second spiral winding, wherein the first level second spiral winding and the first level first spiral winding are interwound around a winding axis,

wherein the second level first trace comprises a second level first spiral winding, the second level second trace comprises a second level second spiral winding, wherein second level second spiral winding and the second level first spiral winding are interwound around the winding axis, wherein the second level first spiral winding is configured in a tracking alignment with the first level first spiral winding, and the second level second spiral winding is configured in a tracking alignment with the first level second spiral winding.

5. The multi-layer capacitor of claim 4, wherein the first level first spiral winding is a first level first rectangular spiral winding, the first level second spiral winding is a first level second rectangular spiral winding, the second level first spiral winding is a second level first rectangular spiral winding, and the second level second spiral winding is a second level second rectangular spiral winding.

6. The multi-layer capacitor of claim 4, wherein the dielectric layer is a first dielectric layer, wherein the multi-layer capacitor further comprises:

a third level spiral capacitor, spaced above the second level spiral capacitor by a second dielectric layer, comprising a third level first spiral winding and a third level second spiral winding, wherein the third level first spiral winding and the third level second spiral winding are interwound around the winding axis, wherein the third level first spiral winding is in a tracking alignment above the second level first spiral winding to form a third parallel plate capacitor, and wherein the third level second spiral winding is configured in a tracking alignment above the second level second spiral winding to form a fourth parallel plate capacitor; and

a fourth level spiral capacitor, spaced above the third level spiral capacitor by a third dielectric layer, comprising a fourth level first spiral winding and a fourth level second spiral winding, wherein the fourth level first spiral winding and the fourth level second spiral winding are interwound around the winding axis, wherein the fourth level first spiral winding is in a tracking alignment with the third level first spiral winding to form a fifth parallel plate capacitor, and wherein the fourth level second spiral winding is configured in a tracking alignment with the third level second spiral winding to form a sixth parallel plate capacitor.

7. The multi-layer capacitor of claim 6, wherein the at least two first posts and the at least two second posts are configured to further extend, normal to the plane, through the second dielectric layer and through the third dielectric layer, and wherein the bridged-post inter-layer interconnect further comprises:

a third level first post coupler, above the second dielectric layer, configured to couple the at least two first posts together and to the third level first spiral winding,

a third level second post coupler, configured to couple the third level second spiral winding to at least one of the at least two second posts;

a fourth level second post coupler, above the third dielectric layer, configured to couple the at least two second posts together and to the fourth level first spiral winding; and

a fourth level first post coupler, configured to couple the fourth level second spiral winding to at least one of the at least two first posts.

8. The multi-layer capacitor of claim 1, wherein the dielectric layer is a first dielectric layer, and wherein the multi-layer capacitor further comprises a third level planar capacitor, spaced above the second level planar capacitor by a second dielectric layer, wherein the second level planar capacitor comprises a third level first trace and a third level second trace, configured adjacent each other and parallel to the plane,

wherein the third level first trace is configured in a tracking alignment above the second level first trace to form a third parallel plate capacitor, and

wherein the third level second trace is configured in a tracking alignment above the second level second trace to form a fourth parallel plate capacitor.

9. The multi-layer capacitor of claim 8, wherein the at least two first posts and the at least two second posts are additionally configured to further extend, normal to the plane, through the second dielectric layer, and wherein the bridged-post inter-layer interconnect further comprises:

a third level first post coupler, above the second dielectric layer, configured to couple the at least two first posts together and to the third level first trace; and

a third level second post coupler, above the second dielectric layer, configured to couple the third level second trace to at least one of the at least two second posts.

10. The multi-layer capacitor of claim 1, wherein the first level first trace includes a first level first trace start, and the first level second trace includes a first level second trace start, wherein the first level second trace start is proximal to the first level first trace start, and

wherein the second level first trace includes a second level first trace start, wherein the second level first trace start is laterally aligned above the first level first trace start, and the second level second trace include a second level second trace start, wherein the second level second trace start is laterally aligned above the first level second trace start.

11. The multi-layer capacitor of claim 10, wherein each of the at least two first posts is proximal to the first level first trace start and to the second level second trace start, and wherein the at least two second posts are proximal to the first level second trace start and to the second level first trace start.

12. The multi-layer capacitor of claim 11, wherein the at least two first posts and the at least two second posts are arranged in an order along a linear axis, wherein the order comprises one of the at least two second posts being adjacent to at least one of the at least two first posts, and another of the at least two first posts being adjacent at least one other of the at least two second posts.

13. The multi-layer capacitor of claim 12, wherein the first level second trace start is laterally spaced from the first level first trace start by a pitch distance, wherein the at least two first posts are each spaced from the first level first trace start by a respective distance, wherein the respective distance is in a range spanning from approximately one-half said pitch distance to approximately said pitch distance.

14. The multi-layer capacitor of claim 11, wherein the first level first post coupler comprises a first level first post bridge and a first level first post stub, wherein the first level first post bridge is configured to couple the at least two first posts together, and the first level first post stub is configured to couple the first level first trace start to at least one of the at least two first posts,

wherein the first level second post coupler comprises a first level second post stub, wherein the first level second post stub is configured to couple the first level second trace start to at least one of the at least two second posts,

wherein the second level second post coupler comprises a second level second post bridge and a second level second post stub, wherein the second level second post bridge is configured to couple the at least two second posts together, and the second level second post stub is configured to couple the second level first trace start to at least one of the at least two second posts,

wherein the second level first post coupler comprises a second level first post stub, wherein the second level first post stub is configured to couple the second level second trace start to at least one of the at least two first posts.

15. The multi-layer capacitor of claim 14, wherein the first level first trace is configured to extend from the first level first trace start to a first level first trace termination, the first level second trace is configured to extend from the first level second trace start to a first level second trace termination, the second level first trace is configured to extend from the second level first trace start to a second level first trace termination, and the second level second trace is configured to extend from the second level second trace start to a second level second trace termination.

16. The multi-layer capacitor of claim 15, wherein the first level second trace termination is proximal to the first level first trace termination, the second level first trace termination is laterally aligned above the first level first trace termination, and the second level second trace termination is laterally aligned above the first level second trace termination.

17. The multi-layer capacitor of claim 16, wherein the first level first trace comprises a first level first spiral winding, configured as winding around a winding axis, wherein the first level second trace comprises a first level second spiral winding, wherein first level second spiral winding is interwound, around the winding axis, with the first level first spiral winding to form the first level planar capacitor as a first level spiral capacitor,

wherein the second level first trace comprises a second level first spiral winding, configured as winding around the winding axis, wherein the second level second trace comprises a second level second spiral winding, wherein the second level second spiral winding is interwound, around the winding axis, with the second level first spiral winding to form the second level planar capacitor as a second level spiral capacitor, and

wherein the winding axis is approximately aligned with the first level first trace start.

18. The multi-layer capacitor of claim 17, wherein the multi-layer capacitor further comprises a second bridged-post inter-layer interconnect, wherein the second bridged-post inter-layer interconnect comprises:

at least two second interconnect first posts and at least two second interconnect second posts, wherein the at least two second interconnect first posts and the at least two second interconnect second posts are configured to extend normal from the plane, at respective positions that are proximal to the first level first trace start and the first level second trace start;

a second interconnect first level second post bridge, a second interconnect first level first post stub and a second interconnect first level second post stub, extending under the dielectric layer, wherein the second interconnect first level second post bridge is configured to couple the at least two second interconnect second posts together, the second interconnect first level first post stub is configured to couple the first level first trace start to at least one of the at least two second interconnect first posts, and the second interconnect first level second post stub is configured to couple the first level first trace termination to at least one of the at least two second interconnect second posts; and

a second interconnect second level first post bridge, a second interconnect second level first post stub and a second interconnect second level second post stub, extending above the dielectric layer, wherein the second interconnect second level first post bridge is configured to couple the at least two second interconnect first posts together, the second interconnect second level first post stub is configured to couple the second level second trace start to at least one of the at least two second interconnect first posts, and the second interconnect second level second post stub is configured to couple the second level first trace start to at least one of the at least two second interconnect second posts.

19. A multi-layer capacitor, comprising:

a first level planar capacitor, comprising a first level first trace and a first level second trace, configured above a plane; and

a second level planar capacitor, spaced above the first level planar capacitor by a dielectric layer, comprising a second level first trace and a second level second trace, wherein the second level first trace is aligned above the first level first trace to form a first parallel plate capacitor, and the second level second trace is aligned above the first level second trace to form a second parallel plate capacitor; and

a bridged-post inter-layer interconnector, comprising

at least two first posts and at least two second posts, wherein the at least two first posts and the at least two first posts are configured to extend normal to the plane and through the dielectric layer adjacent to and outside a perimeter of the first level planar capacitor and a perimeter of the second level planar capacitor,

a first level first post coupler, arranged under the dielectric layer, configured to couple the at least two first posts together and to the first level first trace,

a first level second post coupler, arranged under the dielectric layer, configured to couple the first level second trace to at least one of the at least two second posts,

a second level second post coupler, arranged above second dielectric layer, configured to couple the at least two second posts together and to the second level first trace, and

a second level first post coupler, arranged above second dielectric layer, configured to couple the second level second trace to at least one of the at least two first posts.

20. The multi-layer capacitor of claim 19, wherein the dielectric layer is a first dielectric layer, and wherein the multi-layer capacitor further comprises:

a third level planar capacitor, spaced above the second level planar capacitor by a second dielectric layer, comprising a third level first trace and a third level second trace, wherein the third level first trace is aligned above the second level first trace to form a third parallel plate capacitor, and wherein the third level second trace is aligned above the second level second trace to form a fourth parallel plate capacitor; and

a fourth level planar capacitor, spaced above the third level planar capacitor by a third dielectric layer, comprising a fourth level first trace and a fourth level second trace, wherein the fourth level first trace is aligned above the third level first trace to form a fifth parallel plate capacitor, and the fourth level second trace is aligned above the third level second trace to form a sixth parallel plate capacitor,

wherein the at least two first posts and the at least two second posts are configured to further extend through the second dielectric layer and through the third dielectric layer, and

wherein the bridged-post inter-layer interconnector further comprises

a third level first post coupler, arranged above the second dielectric layer, configured to couple the at least two first posts together and to the third level first trace,

a third level second post coupler, configured to couple the third level second trace to at least one of the at least two second posts,

a fourth level second post coupler, arranged above the third dielectric layer, configured to couple the at least two second posts together and to the fourth level first trace, and

a fourth level first post coupler, configured to couple the fourth level second trace to at least one of the at least two first posts.

21. The multi-layer capacitor of claim 20, wherein the first level planar capacitor is a first level spiral capacitor, the first level first trace comprises a first level first spiral winding and the first level second trace comprises a first level second spiral winding, wherein the first level first spiral winding and the first level second spiral winding are interwound around a winding axis,

wherein the second level planar capacitor is a second level spiral capacitor, the second level first trace comprises a second level first spiral winding and the second level second trace comprises a second level second spiral winding, wherein the second level first spiral winding is in a tracking alignment above the first level first spiral winding, and the second level second spiral winding is in a tracking alignment above the first level second spiral winding,

wherein the third level planar capacitor is a third level spiral capacitor, the third level first trace comprises a third level first spiral winding and the third level second trace comprises a third level second spiral winding, wherein the third level first spiral winding is in a tracking alignment above the second level first spiral winding, and the third level second spiral winding is in a tracking alignment above the second level second spiral winding, and

wherein the fourth level planar capacitor is a fourth level spiral capacitor, the fourth level first trace comprises a fourth level first spiral winding and the fourth level second trace comprises a fourth level second spiral winding, wherein the fourth level first spiral winding is in a tracking alignment above the third level first spiral winding, and the fourth level second spiral winding is in a tracking alignment above the third level second spiral winding.

22. The multi-layer capacitor of claim 21, wherein an outer turn of the first level first spiral winding is an outer periphery of the first level spiral capacitor, an outer turn of the second level first spiral winding is an outer periphery of the second level spiral capacitor, an outer turn of the third level first spiral winding is an outer periphery of the third level spiral capacitor, and an outer turn of the fourth level first spiral winding is an outer periphery of the fourth level spiral capacitor,

wherein the multi-layer capacitor further comprises a plurality of side inter-layer interconnects, each side inter-layer interconnect configured to connect the outer turn of the first level first spiral winding to the outer turn of the third level first spiral winding, and to connect the outer turn of the second level first spiral winding to the outer turn of the fourth level first spiral winding.

23. The multi-layer capacitor of claim 22, wherein each side inter-layer interconnect comprises:

at least two side first posts and at least two side second posts, each extending normal to the plane and comprising at least two side first posts and the at least two side second posts, wherein the at least two side first posts are configured to extend adjacent the outer turn of the first level first spiral winding and adjacent the outer turn of the third level first spiral winding, and the at least two side second posts are configured to extend adjacent the outer turn of the second level first spiral winding and adjacent the outer turn of the fourth level first spiral winding;

at least two first level side stubs, wherein each of the at least two first level side stubs is configured to couple the outer turn of the first level first spiral winding to at least one of the at least two side first posts;

at least two third level side stubs, wherein each of the at least two third level side stubs is configured to couple the outer turn of the third level first spiral winding to at least one of the at least two side first posts;

at least two second level side stubs, wherein each of the at least two second level side stubs is configured to couple the outer turn of the second level first spiral winding to at least one of the at least two side second posts; and

at least two fourth level side stubs, wherein each of the at least two fourth level side stubs is configured to couple the outer turn of the fourth level first spiral winding to at least one of the at least two side second posts.

24. The multi-layer capacitor of claim 21, further comprising at least one interior inter-layer interconnect, wherein the at least one interior inter-layer interconnect is configured to connect an interior turn of the first level first spiral winding to an interior turn of the third level first spiral winding, or to connect an interior turn of the first level second spiral winding to an interior turn of the third level second spiral winding, or both, and wherein the at least one interior inter-layer interconnect is configured to connect an interior turn of the second level first spiral winding to an interior turn of the fourth level first spiral winding, or to connect an interior turn of the second level second spiral winding to an interior turn of the fourth level second spiral winding, or both.

25. A multi-layer capacitor, comprising:

a capacitor stack, wherein the capacitor stack comprises odd level spiral capacitors and even level spiral capacitors, each of the even level spiral capacitors spaced above a corresponding one of the odd level spiral capacitors, wherein each of the odd level spiral capacitors comprises an odd level first spiral winding and an odd level second spiral winding, the odd level first spiral winding and the odd level second spiral winding being interwound about a winding axis, wherein each of the even level spiral capacitors comprises an even level first spiral winding and an even level second spiral winding, the even level first spiral winding and the even level second spiral winding being interwound about the winding axis, and in a tracking alignment with the odd level first spiral winding and the odd level second spiral winding of an underlying one of the odd level spiral capacitors; and

a bridged-post inter-layer interconnect, comprising at least two first posts, and at least two second posts, wherein the at least two first posts and the at least two second posts are configured to extend through the respective dielectric layers adjacent to and outside a perimeter of the odd level spiral capacitors and a perimeter of the even level spiral capacitors, wherein the bridged-post inter-layer interconnect further comprises

adjacent each of the odd level spiral capacitors, an odd level first post coupler and an odd level second post coupler, wherein the odd level first post coupler is configured to couple the at least two first posts together and to the odd level first spiral winding of the odd level spiral capacitor, and the odd level second post coupler is configured to couple the odd level second spiral winding of the odd level spiral capacitor to at least one of the at least two second posts, and

adjacent each of the even level spiral capacitors, an even level first post coupler and an even level second post coupler, wherein the even level second post coupler is configured to couple the at least two second posts together and to the even level first spiral winding of the even level spiral capacitor, and the even level first post coupler is configured to couple the even level second spiral winding of the even level spiral capacitor to at least one of the at least two first posts.

26. The multi-layer capacitor of claim 25, wherein the odd level first spiral winding of each odd level spiral capacitor is configured to extend from an odd level first spiral winding start to an odd level first spiral winding termination, wherein the odd level first spiral winding start is approximately aligned with a winding axis, wherein the winding axis is common to all of the odd level spiral capacitors, and wherein the odd level second spiral winding of each odd level spiral capacitor is configured to extend from an odd level second spiral winding start to an odd level second spiral winding termination, wherein the odd level second spiral winding start is proximal to the odd level first spiral winding start and the odd level second spiral winding termination is proximal to the odd level first spiral winding termination.

27. The multi-layer capacitor of claim 26, wherein the even level first spiral winding of each even level spiral capacitor is configured to extend from an even level first spiral winding start to an even level first spiral winding termination, wherein the even level first spiral winding start is approximately aligned with the winding axis, wherein the winding axis is common to all of the even level spiral capacitors, and wherein the even level second spiral winding of each even level spiral capacitor is configured to extend from an even level second spiral winding start to an even level second spiral winding termination, wherein the even level second spiral winding start is proximal to the even level first spiral winding start and the even level second spiral winding termination is proximal to the even level first spiral winding termination.

28. The multi-layer capacitor of claim 27, wherein the odd level first post coupler comprises an odd level first post bridge and an odd level first post stub, wherein the odd level first post bridge is configured to couple the at least two first posts together, and the odd level first post stub is configured to couple the odd level first spiral winding termination to at least one of the at least two first posts, and

wherein the even level second post coupler comprises an even level second post bridge and an even level second post stub, wherein the even level second post bridge is configured to couple the at least two second posts together, and the even level second post stub is configured to couple the even level first spiral winding termination to at least one of the at least two second posts.

29. The multi-layer capacitor of claim 28, wherein the bridged-post inter-layer interconnect is a first bridged-post inter-layer interconnect, and wherein the multi-layer capacitor further comprises a second bridged-post inter-layer interconnect, wherein the second bridged-post inter-layer interconnect comprises at least two second interconnect first posts and at least two second interconnect second posts, and wherein the second bridged-post inter-layer interconnect further comprises

adjacent each of the odd level spiral capacitors, a second interconnect odd level first post coupler and a second interconnect odd level second post coupler, wherein the second interconnect odd level second post coupler is configured to couple the at least two second interconnect second posts together and to the odd level second spiral winding start of the odd level spiral capacitor, and the second interconnect odd level first post coupler is configured to couple the odd level first spiral winding start of the odd level spiral capacitor to at least one of the at least two second interconnect first posts, and

adjacent each of the even level spiral capacitors, a second interconnect even level first post coupler and a second interconnect even level second post coupler, wherein the second interconnect even level first post coupler is configured to couple the at least two second interconnect first posts together and to the even level first spiral winding start of the even level spiral capacitor, and the second interconnect even level second post coupler is configured to couple the even level second spiral winding start of the even level spiral capacitor to at least one of the at least two second interconnect second posts.

30. A multi-layer capacitor, comprising:

a first level planar capacitor, comprising a first level first trace and a first level second trace, each extending above a plane; and

a second level planar capacitor, spaced above the first level planar capacitor by a dielectric layer, comprising a second level first trace and a second level second trace, wherein the second level first trace is aligned above the first level first trace to form a first parallel plate capacitor, and the second level second trace is aligned above the first level second trace to form a second parallel plate capacitor;

a third level planar capacitor, spaced above the second level planar capacitor by a second dielectric layer, comprising a third level first trace and a third level second trace, wherein the third level first trace is aligned above the second level first trace to form a third parallel plate capacitor, and wherein the third level second trace is aligned above the second level second trace to form a fourth parallel plate capacitor;

a fourth level planar capacitor, spaced above the third level planar capacitor by a third dielectric layer, comprising a fourth level first trace and a fourth level second trace, wherein the fourth level first trace is aligned above the third level first trace to form a fifth parallel plate capacitor, and the fourth level second trace is aligned above the third level second trace to form a sixth parallel plate capacitor; and

means for coupling, in parallel, the first level planar capacitor, the second level planar capacitor, the first parallel plate capacitor, the second parallel plate capacitor, the third parallel plate capacitor, the fourth parallel plate capacitor, the fifth parallel plate capacitor, and the sixth parallel plate capacitor, the means for coupling adjacent to and outside a perimeter of the first level planar capacitor, a perimeter of the second level planar capacitor, a perimeter of the first parallel plate capacitor, a perimeter of the second parallel plate capacitor, a perimeter of the third parallel plate capacitor, a perimeter of the fourth parallel plate capacitor, a perimeter of the fifth parallel plate capacitor, and a perimeter of the sixth parallel plate capacitor.