Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack

• US 9,653,548 B2
• Filed: 04/21/2016
• Issued: 05/16/2017
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Dewey, Gilbert, Radosavljevic, Marko, Pillarisetty, Ravi, Chu-Kung, Benjamin, Mukherjee, Niloy
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US15/135,262
• Publication Number:
  US 20160240612A1
• Time in Patent Office: 390 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

Claims

1. A semiconductor device, comprising:

a bottom barrier layer disposed above a substrate;

a three-dimensional group III-V material body having a channel region, the three-dimensional group III-V material body disposed above the bottom barrier layer;

a trench disposed in the bottom barrier layer below the channel region;

a gate stack comprising;

a first gate dielectric layer disposed on and completely surrounding the channel region;

a second gate dielectric layer disposed on and completely surrounding the first gate dielectric layer, the second gate dielectric layer separate and distinct from the first gate dielectric layer and further disposed along sidewalls of the trench; and

a gate electrode disposed on the second gate dielectric layer and filling the trench; and

source and drain region disposed on either side of the gate stack.

2. The semiconductor device of claim 1, wherein the second gate dielectric layer has a higher dielectric constant than the first gate dielectric layer.

3. The semiconductor device of claim 2, wherein the second gate dielectric layer has a dielectric constant greater than approximately 8 and the first gate dielectric layer has a dielectric constant approximately in the range of 4-8.

4. The semiconductor device of claim 2, wherein the second gate dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO_x), aluminum oxide (AlO_x), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), and lanthanum oxide (La₂O₃), and the first gate dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO_x), silicon oxynitride (SiON), silicon dioxide (SiO₂) and silicon nitride (Si₃N₄).

5. The semiconductor structure of claim 1, wherein the first gate dielectric layer has a thickness approximately in the range of 0.3-2 nanometers, and the second gate dielectric layer has a thickness approximately in the range of 0.5-3 nanometers.

6. The semiconductor structure of claim 1, further comprising:

a top barrier layer disposed above and on either side of the channel region, wherein the second gate dielectric layer is further disposed along sidewalls of the top barrier layer.

7. A method of fabricating a semiconductor device, the method comprising:

forming a bottom barrier layer above a substrate;

forming a three-dimensional group III-V material body above the bottom barrier layer, the three-dimensional group III-V material body having a channel region;

forming a trench in the bottom barrier layer below the channel region;

forming a gate stack, the forming comprising;

forming a first gate dielectric layer on and completely surrounding the channel region;

forming a second gate dielectric layer on and completely surrounding the first gate dielectric layer, the second gate dielectric layer separate and distinct from the first gate dielectric layer and further formed along sidewalls of the trench; and

forming a gate electrode on the second gate dielectric layer and filling the trench; and

forming source and drain region on either side of the gate stack.

8. The method of claim 7, wherein the second gate dielectric layer has a higher dielectric constant than the first gate dielectric layer.

9. The method of claim 8, wherein the second gate dielectric layer has a dielectric constant greater than approximately 8 and the first gate dielectric layer has a dielectric constant approximately in the range of 4-8.

10. The method of claim 8, wherein the second gate dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO_x), aluminum oxide (AlO_x), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), and lanthanum oxide (La₂O₃), and the first gate dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO_x), silicon oxynitride (SiON), silicon dioxide (SiO₂) and silicon nitride (Si₃N₄).

11. The method of claim 7, wherein the first gate dielectric layer is formed to a thickness approximately in the range of 0.3-2 nanometers, and the second gate dielectric layer is formed to a thickness approximately in the range of 0.5-3 nanometers.

12. The method of claim 7, further comprising:

forming a top barrier layer above and on either side of the channel region, wherein the second gate dielectric layer is further formed along sidewalls of the top barrier layer.

13. A semiconductor device, comprising:

a plurality of three-dimensional group III-V material bodies disposed above a substrate;

a gate stack disposed on and completely surrounding channel regions of each of the three-dimensional group III-V material bodies, the gate stack comprising;

a first gate dielectric layer disposed on each of the channel regions;

a second gate dielectric layer disposed on the first gate dielectric layer, the second gate dielectric layer separate and distinct from the first gate dielectric layer, wherein the first gate dielectric layer has a thickness approximately in the range of 0.3-2 nanometers, and the second gate dielectric layer has a thickness approximately in the range of 0.5-3 nanometers; and

a gate electrode disposed on the second gate dielectric layer; and

source and drain regions disposed adjacent to the channel regions of each of the plurality of three-dimensional group III-V material bodies, on either side of the gate stack.

14. The semiconductor structure of claim 13, wherein portions of the source and drain regions are formed within the plurality of three-dimensional group III-V material bodies.

15. The semiconductor structure of claim 13, further comprising:

a bottom barrier layer disposed between the substrate and the plurality of three-dimensional group III-V material bodies.

16. The semiconductor structure of claim 15, wherein a bottom portion of the gate stack is disposed on the bottom barrier layer.

17. The semiconductor device of claim 13, wherein the second gate dielectric layer has a higher dielectric constant than the first gate dielectric layer.

18. The semiconductor device of claim 17, wherein the second gate dielectric layer has a dielectric constant greater than approximately 8, and the first gate dielectric layer has a dielectric constant approximately in the range of 4-8.

19. The semiconductor device of claim 17, wherein the second gate dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO_x), aluminum oxide (AlO_x), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), and lanthanum oxide (La₂O₃), and the first gate dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO_x), silicon oxynitride (SiON), silicon dioxide (SiO₂) and silicon nitride (Si₃N₄).

20. A semiconductor device, comprising:

a plurality of three-dimensional group III-V material bodies disposed above a substrate;

a bottom barrier layer disposed between the substrate and the plurality of three-dimensional group III-V material bodies;

a gate stack disposed on and completely surrounding channel regions of each of the three-dimensional group III-V material bodies, the gate stack comprising;

a first gate dielectric layer disposed on each of the channel regions;

a second gate dielectric layer disposed on the first gate dielectric layer, the second gate dielectric layer separate and distinct from the first gate dielectric layer; and

a gate electrode disposed on the second gate dielectric layer; and

source and drain regions disposed adjacent to the channel regions of each of the plurality of three-dimensional group III-V material bodies, on either side of the gate stack.

21. The semiconductor structure of claim 20, wherein a bottom portion of the gate stack is disposed on the bottom barrier layer.

22. The semiconductor device of claim 20, wherein the second gate dielectric layer has a higher dielectric constant than the first gate dielectric layer.

23. The semiconductor device of claim 22, wherein the second gate dielectric layer has a dielectric constant greater than approximately 8, and the first gate dielectric layer has a dielectric constant approximately in the range of 4-8.

24. The semiconductor device of claim 22, wherein the second gate dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO_x), aluminum oxide (AlO_x), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), and lanthanum oxide (La₂O₃), and the first gate dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO_x), silicon oxynitride (SiON), silicon dioxide (SiO₂) and silicon nitride (Si₃N₄).

25. The semiconductor structure of claim 20, wherein portions of the source and drain regions are formed within the plurality of three-dimensional group III-V material bodies.