Method of manufacturing an insulated gate bipolar transistor with mesa sections between cell trench structures

• US 9,653,568 B2
• Filed: 06/09/2015
• Issued: 05/16/2017
• Est. Priority Date: 09/13/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schulze, Hans-Joachim, Jaeger, Christian, Baburske, Roman, Vellei, Antonio, Philippou, Alexander, Laven, Johannes Georg
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Ivanov, Pavel
• Application Number:
  US14/734,723
• Publication Number:
  US 20150270369A1
• Time in Patent Office: 707 Days
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A method of manufacturing an insulated gate bipolar transistor includes providing trenches extending from a first surface to a layer section in a semiconductor portion, introducing impurities into mesa sections between the trenches, and forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions. The source regions are electrically connected to an emitter electrode. The second portions have a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of the doped layer. The first portions extend from the body regions to the layer section, respectively.

Claims

1. A method of manufacturing an insulated gate bipolar transistor, the method comprising:

forming trenches extending from a first surface to a layer section in a semiconductor portion;

introducing impurities into mesa sections between the trenches; and

forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions, the source regions electrically connected to an emitter electrode, the second portions having a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of doped regions, wherein the first portions extend continuously along sidewalls of the mesa regions from the body regions to the layer section, respectively.

2. The method of claim 1, wherein introducing the impurities comprises implanting the impurities into the mesa sections at one or more implant angles with regard to a normal on the first surface, wherein the implant angle(s) is/are greater than arctan(W/L) with W being a width of the trenches and L being a vertical extension of the trenches.

3. The method of claim 1, wherein introducing the impurities comprises a plasma diffusion process diffusing the impurities through sidewalls of the mesa sections.

4. The method of claim 1, further comprising:

filling, before introducing the impurities, the trenches, which comprise first and second trenches;

providing an implant mask covering the filled first trenches and exposing the filled second trenches;

recessing at least partly a fill in the second trenches using the implant mask as an etch mask; and

introducing the impurities by ion implantation that uses the implant mask.

5. A method of manufacturing an insulated gate bipolar transistor, the method comprising:

forming provisional trenches extending from a first surface into a semiconductor portion;

introducing impurities into mesa sections between the provisional trenches;

recessing the provisional trenches to a layer section in the semiconductor portion after the impurities are introduced in a bottom portion of the provisional trenches; and

forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions, the source regions electrically connected to an emitter electrode, the second portions having a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of the doped regions, wherein the first portions extend continuously, along sidewalls of the mesa sections from the body regions to the layer section, respectively.