Replacement metal gate including dielectric gate material

• US 9,653,573 B2
• Filed: 08/17/2015
• Issued: 05/16/2017
• Est. Priority Date: 01/30/2014
• Status: Expired due to Fees

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation
• Inventors: Jang, Linus, Kanakasabapathy, Sivananda K., Mehta, Sanjay C., Seo, Soon-Cheon, Sreenivasan, Raghavasimhan
• Primary Examiner(s): Au, Bac
• Assistant Examiner(s): NGUYEN, SOPHIA T
• Application Number:
  US14/827,510
• Publication Number:
  US 20150357434A1
• Time in Patent Office: 638 Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 : using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66575 : where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate
• CPC Class Codes: H01L 29/7855 : with at least two independent gates

Abstract

A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming at least one semiconductor fin on a semiconductor substrate;

forming an etch stop layer on an upper surface of the at least one semiconductor fin;

forming a plurality of dummy gate elements on the etch stop layer such that the etch stop layer is located between the at least one semiconductor fin and each dummy gate element among the plurality of dummy gate elements, each dummy gate element formed from a dielectric material selected from a group comprising of boron carbide (BC), carbon (C), silicon dioxide (SiO₂), and a silicon boron carbide material that contains nitrogen (SiB;

C(N)), and each dummy gate element having a hardmask gate cap formed atop the dielectric material;

depositing a high-dielectric constant layer directly against an outer surface of each dummy gate element and depositing a spacer layer on the high-dielectric constant layer;

performing a first etching process that etches the spacer layer to form a spacer on each sidewall of dummy gate elements and exposes an upper portion of the high-dielectric constant layer;

performing a pre-clean process that removes a portion of the etch stop layer located between each dummy gate element so as to form a cavity that exposes a portion of the at least one semiconductor fin between each dummy gate element;

performing an epitaxial growth process that grows an epitaxial semiconductor material on the exposed portion of the at least one semiconductor fin between each dummy gate element;

performing a second etching process different from the first etching process that selectively etches the upper portion of the high-dielectric constant layer to expose each hardmask gate cap;

depositing a contact dielectric layer that fills a void between the spacers, and covers an outer surface of the spacers and an upper portion of the dummy gate elements;

performing a planarization process selective to one of boron carbide (BC), carbon (C), silicon dioxide (SiO₂), and a silicon boron carbide material that contains nitrogen (SiB;

C(N)) such that the dummy gate element is used as an etch stop element so as to remove the hardmask gate caps and form an upper surface of the contact dielectric layer flush with an upper surface of each spacer and an upper surface of each dummy gate element;

removing the dummy gate elements to form a trench between a respective pair of spacers; and

performing a third etching process after removing the dummy gates elements to remove a portion of the high-dielectric constant material from the sidewalls of the spacers such that a remaining portion of the high-dielectric constant material is interposed between the spacers and the etch stop layer; and

depositing a gate material in the trenches to form a metal gate element that contacts the spacers, the remaining portion of high-dielectric constant material and the etch stop layer.