Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices

• US 9,653,583 B1
• Filed: 08/02/2016
• Issued: 05/16/2017
• Est. Priority Date: 08/02/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zhao, Wei, Wang, Haiting, Shen, Hongliang, Hu, Zhenyu, Chi, Min-Hwa
• Primary Examiner(s): Mulpuri, Savitr
• Application Number:
  US15/226,165
• Time in Patent Office: 287 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

One illustrative method disclosed herein includes, among other things, forming a first gate structure above a fin, forming epi semiconductor material on the fin, performing at least one first etching process through a patterned sacrificial layer of material to remove at least a gate cap layer and sacrificial gate materials of the first gate structure so as to define a first isolation cavity that exposes the fin while leaving the second gate structure intact, performing at least one second etching process through the first isolation cavity to remove at least a portion of a vertical height of the fin and thereby form a first isolation trench, removing the patterned sacrificial layer of material, and forming a layer of insulating material above the epi semiconductor material and in the first isolation trench and in the first isolation cavity.

Claims

1. A method of forming a diffusion break for a FinFET device comprising a fin formed in a semiconductor substrate, the method comprising:

forming a first gate structure above said fin, said first gate structure comprising sacrificial gate materials, a sidewall spacer and a gate cap layer;

forming epi semiconductor material on exposed portions of said fin;

forming a patterned sacrificial layer of material above said epi semiconductor material, wherein said patterned sacrificial layer of material covers a second gate structure while exposing at least said gate cap layer of said first gate structure;

performing at least one first etching process through said patterned sacrificial layer of material to remove at least said gate cap layer and said sacrificial gate materials of said first gate structure so as to define a first isolation cavity that exposes said fin while leaving said second gate structure intact;

performing at least one second etching process through said first isolation cavity to remove at least a portion of a vertical height of said fin and thereby form a first isolation trench;

removing said patterned sacrificial layer of material; and

forming a layer of insulating material above said epi semiconductor material and in said first isolation trench and in said first isolation cavity.

2. The method of claim 1, wherein said second gate structure comprises sacrificial gate materials, a sidewall spacer and a gate cap layer and wherein the method further comprises:

removing at least said gate cap layer and at least a portion of said sacrificial gate materials of said second gate structure so as to define a replacement gate cavity; and

forming a replacement gate structure in said replacement gate cavity.

3. The method of claim 1, wherein said layer of insulating material substantially fills said first isolation trench and said first isolation cavity.

4. The method of claim 3, wherein forming said layer of insulating material comprises:

forming said layer of insulating material above said substrate so as to over-fill said first isolation trench and said first isolation cavity; and

performing at least one planarization process so as to planarize an upper surface of said layer of insulating material with an upper surface of said gate cap layer of said second gate structure, thereby leaving a first portion of said layer of insulating material positioned in said first isolation trench and in said first isolation cavity.

5. The method of claim 3, wherein said first isolation cavity is partially defined by said sidewall spacer of said first gate structure.

6. The method of claim 1, wherein said first isolation trench is formed so as to remove the entire vertical height of said fin and to extend into said substrate.

7. A method of forming a diffusion break for a FinFET device comprising a fin formed in a semiconductor substrate, the method comprising:

forming first, second and third gate structures above said fin, said second gate structure being laterally positioned between said first and third gate structures, each of said first, second and third gate structures comprising sacrificial gate materials, a sidewall spacer and a gate cap layer;

forming epi semiconductor material on exposed portions of said fin;

forming a patterned sacrificial layer of material above said epi semiconductor material, wherein said patterned sacrificial layer of material covers said second gate structure while exposing at least said gate cap layer of said first and third gate structures;

performing at least one first etching process through said patterned sacrificial layer of material to remove at least said gate cap layer and said sacrificial gate materials of said first and third gate structures so as to define first and second isolation cavities that expose said fin while leaving said second gate structure intact;

performing at least one second etching process through said first and second isolation cavities to remove at least a portion of a vertical height of said fin and thereby form first and second isolation trenches;

removing said patterned sacrificial layer of material; and

forming a layer of insulating material above said epi semiconductor material in said first and second isolation trenches and in said first and second isolation cavities.

8. The method of claim 7, further comprising:

removing at least said gate cap layer and at least a portion of said sacrificial gate materials of said second gate structure so as to define a replacement gate cavity; and

forming a replacement gate structure in said replacement gate cavity.

9. The method of claim 7, wherein said layer of insulating material substantially fills said first and second isolation trenches and said first and second isolation cavities.

10. The method of claim 7, wherein forming said layer of insulating material comprises:

forming said layer of insulating material above said substrate so as to over-fill said first and second isolation trenches and said first and second isolation cavities; and

performing at least one planarization process so as to planarize an upper surface of said layer of insulating material with an upper surface of said gate cap layer of said second gate structure, thereby leaving a first portion of said layer of insulating material positioned in said first isolation trench and in said first isolation cavity and a second portion of said layer of insulating material positioned in said second isolation cavity and in said second isolation trench.

11. The method of claim 7, wherein said first and second isolation cavities are partially defined by said sidewall spacer of said first and third gate structures, respectively.

12. The method of claim 7, wherein said first and second isolation trenches are formed so as to remove the entire vertical height of said fin and to extend into said substrate.

13. The method of claim 7, wherein forming said patterned sacrificial layer of material comprises:

forming a sacrificial layer of material on and in contact with said epi semiconductor material;

forming a patterned etch mask above said sacrificial layer of material; and

performing an etching process through said patterned etch mask to remove exposed portions of said sacrificial layer of material.

14. The method of claim 13, wherein performing said at least one first etching process comprises:

performing at least one third etching process so as to remove said gate cap layer and a portion of a vertical height of said sidewall spacer for each of said first and third gate structures, wherein at the completion of said at least one first etching process, an upper surface of said sacrificial gate materials of said first and third gate structures is exposed; and

performing at least one fourth etching process so as to remove substantially all of said sacrificial gate materials of said first and third gate structures so as to thereby define said first and second isolation cavities.

15. The method of claim 7, wherein said sacrificial layer of material comprises one of SOH, OPL or silicon dioxide and said layer of insulating material comprises silicon dioxide.

16. The method of claim 7, wherein said sacrificial gate materials of said first, second and third gate structures are comprised of one of polysilicon or amorphous silicon and a layer of silicon dioxide.

17. The method of claim 7, wherein said replacement gate structure comprises a high-k gate insulation layer and at least one layer of metal.

18. The method of claim 13, wherein said at least one second etching process is performed prior to removing said patterned etch mask.

19. The method of claim 13, wherein said at least one second etching process is performed after removing said patterned etch mask.

20. The method of claim 7, wherein, prior to forming said epi semiconductor material on said exposed portions of said fin, the method comprises etching a trench into said fin and forming said epi semiconductor material in said trench in said fin.

21. A method of forming a diffusion break for a FinFET device comprising a fin formed in a semiconductor substrate, the method comprising:

forming first, second and third gate structures above said fin, said second gate structure being laterally positioned between said first and third gate structures, each of said first, second and third gate structures comprising sacrificial gate materials, a sidewall spacer and a gate cap layer;

forming epi semiconductor material on exposed portions of said fin;

forming a sacrificial layer of material on and in contact with said epi semiconductor material, said sacrificial layer of material having an upper surface that is positioned at a level that is above a level of an upper surface of said gate cap layer of said first, second and third gate structures;

forming a patterned etch mask above said sacrificial layer of material;

performing an etching process through said patterned etch mask to remove exposed portions of said sacrificial layer of material so as to thereby define a patterned sacrificial layer of material, wherein said patterned sacrificial layer of material covers said second gate structure while exposing at least said gate cap layer of said first and third gate structures;

performing at least one first etching process so as to remove said gate cap layer and a portion of a vertical height of said spacer for each of said first and third gate structures, wherein, at the completion of said at least one first etching process, an upper surface of said sacrificial gate materials of said first and third gate structures is exposed;

performing at least one second etching process so as to remove substantially all of said sacrificial gate materials of said first and third gate structures so as to define first and second isolation cavities that expose said fin while leaving said second gate structure intact;

performing at least one third etching process through said first and second isolation cavities to remove at least a portion of a vertical height of said fin and thereby form first and second isolation trenches;

removing said patterned sacrificial layer of material; and

forming a layer of insulating material above said epi semiconductor material, said layer of insulating material substantially filling said first and second isolation trenches and said first and second isolation cavities.

22. The method of claim 21, further comprising:

removing at least said gate cap layer and at least a portion of said sacrificial gate materials of said second gate structure so as to define a replacement gate cavity; and

forming a replacement gate structure in said replacement gate cavity.

23. The method of claim 21, wherein forming said layer of insulating material comprises:

forming said layer of insulating material above said substrate so as to over-fill said first and second isolation trenches and said first and second isolation cavities; and

performing at least one planarization process so as to planarize an upper surface of said layer of insulating material with an upper surface of said gate cap layer of said second gate structure, thereby leaving a first portion of said layer of insulating material positioned in said first isolation trench and in said first isolation cavity and a second portion of said layer of insulating material positioned in said second isolation cavity and in said second isolation trench.

24. The method of claim 21, wherein said first and second isolation cavities are partially defined by said sidewall spacer of said first and third gate structures, respectively.

25. The method of claim 24, wherein said first and second isolation trenches are formed so as to remove the entire vertical height of said fin and to extend into said substrate.