High speed communication jack

• US 9,653,847 B2
• Filed: 12/01/2015
• Issued: 05/16/2017
• Est. Priority Date: 01/11/2013
• Status: Active Grant

• Current Assignee: Sentinel Connector Systems, Inc.
• Original Assignee: Sentinel Connector Systems, Inc.
• Inventors: Robinson, Brett
• Primary Examiner(s): GUSHI, ROSS N
• Application Number:
  US14/955,166
• Publication Number:
  US 20160079708A1
• Time in Patent Office: 532 Days
• CPC Class Codes: H01R 13/6466 on substrates, e.g. printed circuit boards [PCB]
• CPC Class Codes: H01R 13/6474 by variation of conductive properties, e.g. by dimension variations
• CPC Class Codes: H01R 13/6581 Shield structure
• CPC Class Codes: H01R 13/6658 on printed circuit board H01R13/6666 - H01R13/6691 take precedence
• CPC Class Codes: H01R 2107/00 Four or more poles
• CPC Class Codes: H01R 24/64 for high frequency, e.g. RJ 45
• CPC Class Codes: H05K 1/024 Dielectric details, e.g. changing the dielectric material around a transmission line
• CPC Class Codes: H05K 1/0251 related to vias or transitions between vias and transmission lines
• CPC Class Codes: H05K 1/09 Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A high speed communication jack including a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug, a shielding case surrounding the housing, a rigid circuit board in the housing having a substrate, a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing, a plurality of traces on a middle layer in the substrate, with each trace extending from a corresponding one of the plurality of vias, a first shielding layer on a first side of the middle layer in the substrate, a second shielding layer on a second side of the middle layer in the substrate, and a third shielding layer adjacent to the second shielding layer.

Claims

1. A high speed communication jack including:

a housing including a port for accepting a plug, the port including a plurality of first pins each connected to a corresponding signal line in the plug;

a shielding case surrounding the housing;

a rigid circuit board in the housing having

a substrate,

a plurality of vias extending through the substrate with each via being configured to accommodate a pin from a plurality of second pins on the housing,

a plurality of traces on a middle layer in the substrate, with each trace extending from a corresponding one of the plurality of vias;

a first shielding layer on a first side of the middle layer in the substrate;

a second shielding layer on a second side of the middle layer in the substrate; and

a third shielding layer adjacent to the second shielding layer.

2. The jack of claim 1 wherein, when energized, each trace of the plurality of traces is differentially matched to a second adjacent trace of the plurality of traces.

3. The jack of claim 2 wherein the impedance value of a first trace in a matched pair of traces is adjusted to be substantially equal to the impedance value of the second trace in the matched pair of traces.

4. The jack of claim 3 wherein the width, height or length of each trace in matched set of traces is adjusted such that the impedance of the first trace matches the impedance of the second trace.

5. The jack of claim 3 wherein the impedance of the first trace and second trace are adjusted such that the traces are matched when a first signal is transmitted on the first trace and a second signal is transmitted on the second trace.

6. The jack of claim 1 wherein a capacitor is formed in each via by a trace layer and a return signal layer embedded in a dielectric layer.

7. The jack of claim 6 wherein a distance between the return signal layer and the trace layer is adjusted such that the capacitor has a value of between approximately 0.1 pf and approximately 0.5 pf.

8. The jack of claim 6 wherein a second return signal layer is formed in the dielectric layer below the first return signal layer to form a second capacitor.

9. The jack of claim 8 wherein the distance between the first signal layer and second signal layer is adjusted to adjust the value of the second capacitor between 0.1 pf and 0.5 pf.

10. The jack of claim 6 wherein the capacitor, trace and return signal layer form a common mode filter with the matched set of traces.

11. The jack of claim 10 wherein the value of the capacitor is adjusted such that the common mode filter prevents reflections of signals from the matched traces .

12. The jack of claim 11 including a second shielding tab on a side of the substrate opposite the first shielding.

13. The jack of claim 1 wherein the traces are plated in gold.

14. The jack of claim 1, wherein the substrate includes a dielectric material having a dielectric constant greater than 3.0.

15. A high speed communication jack comprising a standard RJ45 housing having a port for accepting a plug, the port including a plurality of first pins connected to a corresponding signal line in the plug, the jack comprising:

a shielding case surrounding the housing

a rigid circuit board on the lower portion of the housing having

a substrate,

a plurality of vias extending through the substrate with each via being configured to accommodate a pin from second plurality of pins on the housing,

a plurality of traces on a middle layer of the substrate, with each trace extending from a corresponding one of the plurality of vias, and

a first shielding layer on a first side of the middle layer in the substrate;

a second shielding layer on a second side of the middle layer in the substrate; and

a third shielding layer adjacent to the second shielding layer.

16. A method of forming a high speed communication jack, the method including:

forming a first grounding layer,

forming a second layer of a dielectric material on a side of the first layer,

forming a third layer on a side of the second layer opposite the first layer and having a grounding plane made from a conductive material;

forming a fourth layer on a side of the third layer opposite the second layer and made of a dielectric material;

forming a fifth layer on a side of the fourth layer opposite the third layer and having a grounding plane made of a conductive material;

forming a sixth layer formed on a side of the fifth layer opposite the fourth layer and made of a dielectric material;

forming a seventh layer formed on a side of the sixth layer opposite the fifth layer and having a grounding plane made of a conductive material; and

forming vias through the first layer, second layer, third layer, fourth layer, fifth layer, sixth layer and seventh layer,

wherein the third layer includes a plurality of traces extending from each via.

17. A high speed communication jack including:

a housing including a port for accepting a plug, the port including a plurality of first pins each connected to a corresponding signal line in the plug;

a shielding case surrounding the housing

a multilayer rigid circuit board in the housing having

a first grounding layer,

a second layer of a dielectric material on a side of the first layer,

a third layer on a side of the second layer opposite the first layer and having a grounding plane made from a conductive material;

a fourth layer on a side of the third layer opposite the second layer and made of a dielectric material;

a fifth layer on a side of the fourth layer opposite the third layer and having a grounding plane made of a conductive material;

a sixth layer formed on a side of the fifth layer opposite the fourth layer and made of a dielectric material;

a seventh layer formed on a side of the sixth layer opposite the fifth layer and having a grounding plane made of a conductive material; and

a plurality of vias extending through the first, second, third, fourth, fifth sixth and seventh layers, with each via being configured to accommodate a pin from a plurality of second pins on the housing,

wherein the third layer includes a plurality of traces extending from each via.

18. The jack of claim 17 wherein a capacitor is formed in each via by the combination of one of the plurality of traces on the first layer, the second layer and the third layer.

19. The jack of claim 18 wherein the depth of the second layer is adjusted such that the capacitor in each via has a value of between approximately 0.1 pf and approximately 0.5 pf.

20. The jack of claim 17 including a plurality of grounding vias formed through the first, second, third, fourth, fifth sixth and seventh layers.