Silicon photonics modulator driver

• US 9,654,061 B2
• Filed: 04/29/2015
• Issued: 05/16/2017
• Est. Priority Date: 10/20/2014
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Lakshmikumar, Kadaba, Appel, Craig
• Primary Examiner(s): Nguyen, Khanh V
• Assistant Examiner(s): NGUYEN, KHIEM D
• Application Number:
  US14/698,974
• Publication Number:
  US 20160112016A1
• Time in Patent Office: 748 Days
• Field of Search: 330253, 330258
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/086 with FET's
• CPC Class Codes: H03F 2200/135 there being a feedback over one or more internal stages in the global amplifier
• CPC Class Codes: H03F 2200/75 the amplifier stage being a common source configuration MOSFET
• CPC Class Codes: H03F 2203/45026 One or more current sources are added to the amplifying transistors in the differential amplifier
• CPC Class Codes: H03F 2203/45082 the common mode signal being taken or deducted from the one or more outputs of the differential amplifier
• CPC Class Codes: H03F 2203/45088 the resulting deducted common mode signal being added to or controls the differential amplifier, and being a voltage signal
• CPC Class Codes: H03F 2203/45116 Feedback coupled to the input of the differential amplifier
• CPC Class Codes: H03F 2203/45208 the dif amp being of the long tail pair type, one current source being coupled to the common emitter of the amplifying transistors
• CPC Class Codes: H03F 2203/45221 the output signal being taken from the two complementary outputs of the differential amplifier
• CPC Class Codes: H03F 2203/45336 the AAC comprising one or more resistors as feedback circuit elements
• CPC Class Codes: H03F 2203/45402 the CMCL comprising a buffered addition circuit, i.e. the signals are buffered before addition, e.g. by a follower
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 2203/45434 the CMCL output control signal being a voltage signal
• CPC Class Codes: H03F 2203/45436 the CMCL output control signal being a voltage signal and being buffered before used to control
• CPC Class Codes: H03F 2203/45481 the CSC comprising only a direct connection to the supply voltage, no other components being present
• CPC Class Codes: H03F 2203/45594 the IC comprising one or more resistors, which are not biasing resistor
• CPC Class Codes: H03F 2203/45604 the IC comprising a input shunting resistor
• CPC Class Codes: H03F 2203/45642 the LC, and possibly also cascaded stages following it, being (are) controlled by the common mode signal derived to control a dif amp
• CPC Class Codes: H03F 2203/45648 the LC comprising two current sources, which are not cascode current sources
• CPC Class Codes: H03F 2203/45664 : the LC comprising one or more cascaded inverter stages as output stage at one output of the dif amp circuit
• CPC Class Codes: H03F 3/08 : controlled by light
• CPC Class Codes: H03F 3/45076 : characterised by the way of implementation of the active amplifying circuit in the differential amplifier
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45659 : Controlling the loading circuit of the differential amplifier

Abstract

Embodiments generally relate to a conversion arrangement, a driver arrangement, and a method of producing a complementary complementary metal-oxide-semiconductor (CMOS) output signal for driving a modulator device. The conversion arrangement includes a differential amplifier configured to produce a first amplified signal based on the differential input signal, and at least two transimpedance amplifiers (TIAs) coupled with respective outputs of the differential amplifier and configured to produce a second amplified signal based on the first amplified signal. Respective bias voltages for the TIAs are based on the first amplified signal. The conversion arrangement further includes a common-mode feedback arrangement coupled with outputs of the TIAs and configured to control the first amplified signal based on the second amplified signal, thereby controlling the bias voltages, wherein the complementary CMOS output signal is based on the second amplified signal.

Claims

1. A conversion arrangement for converting a differential input signal to a complementary metal-oxide-semiconductor (CMOS) output signal, the conversion arrangement comprising:

a differential amplifier configured to produce a first amplified signal based on the differential input signal, wherein the differential amplifier includes;

a first pair of MOS devices having a first conductivity type, each MOS device of the first pair configured to receive one differential input of the differential input signal; and

a second pair of MOS devices having a second conductivity type, each MOS device of the second pair operating as a current source load for a respective MOS device of the first pair;

at least two transimpedance amplifiers (TIAs) coupled with respective differential outputs of the differential amplifier and configured to produce a second amplified signal based on the first amplified signal, wherein respective bias voltages for the at least two TIAs are based on the first amplified signal; and

a common-mode feedback arrangement coupled with outputs of the at least two TIAs and configured to control the first amplified signal based on the second amplified signal, wherein the common-mode feedback arrangement is coupled with a gate of each MOS device of the second pair in the differential amplifier to control the first amplified signal, and

wherein the CMOS output signal is based on the second amplified signal.

2. The conversion arrangement of claim 1, further comprising an inverter amplification arrangement coupled with an output of the TIAs and configured to produce a rail-to-rail CMOS output signal based on the second amplified signal.

3. The conversion arrangement of claim 2, wherein the inverter amplification arrangement includes one or more cross-coupled inverter stages.

4. The conversion arrangement of claim 1, wherein the differential input signal is a current-mode logic (CML) signal.

5. The conversion arrangement of claim 1, wherein each of the at least two TIAs includes a respective inverter.

6. The conversion arrangement of claim 5, wherein each of the bias voltages is controlled to approximately equal a trip point of the respective inverter.

7. A driver arrangement configured to receive a differential input signal and to produce a complementary metal-oxide-semiconductor (CMOS) output signal for driving a modulator device, the driver arrangement comprising:

a conversion arrangement configured to;

amplify, at a differential amplification stage, the differential input signal to produce a first amplified signal, wherein the differential amplification stage includes;

a first pair of MOS devices having a first conductivity type, each MOS device of the first pair configured to receive one differential input of the differential input signal; and

a second pair of MOS devices having a second conductivity type, each MOS device of the second pair operating as a current source load for a respective MOS device of the first pair;

amplify, using at least two transimpedance amplifiers (TIAs) coupled with respective differential outputs of the differential amplification stage, the first amplified signal to produce a second amplified signal, wherein respective bias voltages for the at least two TIAs are based on the first amplified signal; and

produce, based on the second amplified signal and using a feedback arrangement coupled with the differential amplification stage, a control signal for the differential amplification stage, wherein the feedback arrangement is coupled with a gate of each MOS device of the second pair in the differential amplification stage to control the first amplified signal, and

wherein application of the control signal to the differential amplification stage operates to control the bias voltages for the TIAs.

8. The driver arrangement of claim 7, wherein the conversion arrangement is further configured to, at a second inverter amplification stage coupled with an output of the TIAs, produce a rail-to-rail CMOS output signal based on the second amplified signal.

9. The driver arrangement of claim 7, further comprising a data multiplexing arrangement coupled with an output of the conversion arrangement.

10. The driver arrangement of claim 7, further comprising an output amplification stage coupled with an output of the conversion arrangement.

11. The driver arrangement of claim 7, wherein the differential input signal is a current-mode logic (CML) signal.

12. The driver arrangement of claim 7, wherein the modulator device is a silicon-insulator-silicon capacitor (SISCAP) device.

13. The driver arrangement of claim 7,

wherein each of the at least two TIAs includes a respective inverter, and

wherein each of the bias voltages is controlled to approximately equal a trip point of the respective inverter.

14. A method of producing a complementary metal-oxide-semiconductor (CMOS) output signal for driving a modulator device, the method comprising:

receiving a differential input signal;

amplifying, using a differential amplifier, the differential input signal to produce a first amplified signal, wherein the differential amplifier includes;

a first pair of MOS devices having a first conductivity type, each MOS device of the first pair configured to receive one differential input of the differential input signal; and

a second pair of MOS devices having a second conductivity type, each MOS device of the second pair operating as a current source load for a respective MOS device of the first pair;

amplifying, using transimpedance amplifiers (TIAs) coupled with respective outputs of the differential amplifier, the first amplified signal to produce a second amplified signal, wherein respective bias voltages for the TIAs are based on the first amplified signal;

producing, based on the second amplified signal and using a feedback arrangement coupled with the differential amplifier, a control signal for the differential amplifier, wherein the feedback arrangement is coupled with a gate of each MOS device of the second pair in the differential amplifier to control the first amplified signal; and

applying the control signal to the differential amplifier, thereby controlling the bias voltages for the TIAs,

wherein the CMOS output signal is based on the second amplified signal.

15. The method of claim 14, further comprising:

amplifying, using an inverter amplification arrangement coupled with an output of the TIAs, the second amplified signal to produce a rail-to-rail CMOS output signal.

16. The method of claim 15, wherein the amplification using the differential amplifier, the TIAs, and the inverter amplification arrangement is performed within a conversion stage to produce the rail-to-rail CMOS output signal, the method further comprising, in one or more separate stages, one or more of:

performing data multiplexing on the rail-to-rail CMOS output signal; and

performing an output amplification of the rail-to-rail CMOS output signal.

17. The method of claim 14, wherein the differential input signal is a current-mode logic (CML) signal.

18. The method of claim 14, wherein the modulator device is a silicon-insulator-silicon capacitor (SISCAP) device.

19. The method of claim 14, wherein each of the TIAs includes a respective inverter, and

wherein each of the bias voltages is controlled to approximately equal a trip point of the respective inverter.