Integrated circuit power rail multiplexing

• US 9,654,101 B2
• Filed: 07/30/2015
• Issued: 05/16/2017
• Est. Priority Date: 07/30/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Vilangudipitchai, Ramaprasath, Kumar, Dorav, Cao, Lipeng, Bhan, Divjyot
• Primary Examiner(s): Cole, Brandon S
• Application Number:
  US14/814,409
• Publication Number:
  US 20170033796A1
• Time in Patent Office: 656 Days
• Field of Search: 327365-508
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

Claims

1. An integrated circuit comprising:

a first power rail;

a second power rail;

a load power rail;

a first set of transistors including first transistors that are coupled between the first power rail and the load power rail, each first transistor disposed in one of multiple power-multiplexer tiles, the power-multiplexer tiles configured in a chained arrangement;

a second set of transistors including second transistors that are coupled between the second power rail and the load power rail, each second transistor disposed in one of the power-multiplexer tiles; and

power-multiplexer circuitry configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors in a first direction along the chained arrangement and then sequentially turning on the second transistors of the second set of transistors in a second direction along the chained arrangement, the second direction opposite the first direction, and configured to switch access to power for the load power rail from the second power rail to the first power rail by sequentially turning off the second transistors of the second set of transistors in the first direction along the chained arrangement and then sequentially turning on the first transistors of the first set of transistors in the second direction along the chained arrangement.

2. The integrated circuit of claim 1, wherein the power-multiplexer circuitry comprises self-timed circuitry.

3. The integrated circuit of claim 2, wherein an operational timing of the self-timed circuitry is independent of a periodic clock signal.

4. The integrated circuit of claim 2, wherein the self-timed circuitry comprises multiple circuit devices that have a joint operational timing that is based on an intrinsic speed of individual ones of the multiple circuit devices.

5. The integrated circuit of claim 1, wherein the power-multiplexer circuitry includes a configurable delay device that has an adjustable delay to control a delay between turning off one of the first transistors of the first set of transistors and turning off a sequentially next one of the first transistors of the first set of transistors.

6. The integrated circuit of claim 1, wherein at least a portion of the power-multiplexer circuitry is distributed across the chained arrangement of the multiple power-multiplexer tiles.

7. The integrated circuit of claim 1, wherein:

the power-multiplexer circuitry includes a set of delay circuits; and

a respective delay circuit of the set of delay circuits is coupled between a respective first transistor of the first set of transistors and a respective second transistor of the second set of transistors.

8. The integrated circuit of claim 7, wherein the respective delay circuit is configured to prevent the respective second transistor from being turned on until the respective first transistor is turned off.

9. The integrated circuit of claim 1, further comprising:

a voltage detector;

configured to detect a higher voltage between a first voltage corresponding to the first power rail and a second voltage corresponding to the second power rail; and

configured to power at least part of the power-multiplexer circuitry using the higher voltage.

10. The integrated circuit of claim 1, further comprising:

a third power rail; and

a third set of transistors including third transistors that are coupled between the third power rail and the load power rail, each third transistor disposed in one of the multiple power-multiplexer tiles,

wherein the power-multiplexer circuitry is further configured to switch access to power for the load power rail from the first power rail to the third power rail by sequentially turning off the first transistors and then sequentially turning on the third transistors.

11. The integrated circuit of claim 10, wherein the power-multiplexer circuitry includes a power rail selection decoder that is configured to decode a power rail selection signal, the power rail selection signal indicative of a power source for the load power rail.

19. The method of claim 1, further comprising:

sequentially turning off the second transistors of the second set of transistors, the second transistors turned off in the first direction along the chained arrangement;

after sequentially turning off the second transistors, sequentially turning on third transistors of a third set of transistors, the third transistors coupled to a third power rail that corresponds to a third voltage, each third transistor disposed in one of the power-multiplexer tiles, the third transistors turned on in the second direction along the chained arrangement; and

supplying power to the circuit load at the third voltage using the third transistors.

12. An integrated circuit comprising:

a first power rail;

a second power rail;

a load power rail;

a first set of transistors including first transistors that are coupled between the first power rail and the load power rail, each first transistor disposed in one of multiple power-multiplexer tiles, the power-multiplexer tiles configured in a chained arrangement;

a second set of transistors including second transistors that are coupled between the second power rail and the load power rail, each second transistor disposed in one of the power-multiplexer tiles; and

means for switching access to power for the load power rail from the first power rail to the second power rail, including;

means for sequentially turning off the first transistors of the first set of transistors in a first direction along the chained arrangement; and

means for sequentially turning on the second transistors of the second set of transistors after the first transistors of the first set of transistors are off, the second transistors turned on in a second direction along the chained arrangement, the second direction opposite the first direction.

13. The integrated circuit of claim 12, wherein the means for switching access to power for the load power rail further includes means for decoding a power rail selection signal, which is indicative of a selected power source for the load power rail, to cause one transistor to be on and at least one transistor to be off per power-multiplexer tile of multiple power-multiplexer tiles.

14. The integrated circuit of claim 12, wherein:

the means for switching access to power for the load power rail further includes means for propagating a power rail selection signal to the power-multiplexer tiles; and

the means for sequentially turning off the first transistors is configured to operate responsive to the power rail selection signal.

15. The integrated circuit of claim 12, wherein:

the means for switching access to power for the load power rail further includes means for propagating a transistor operational state feedback signal to the power-multiplexer tiles; and

the means for sequentially turning on the second transistors is configured to operate responsive to the transistor operational state feedback signal.

16. The integrated circuit of claim 12, wherein:

the first power rail corresponds to a first voltage;

the second power rail corresponds to a second voltage; and

the means for switching access to power for the load power rail comprises means for switching access to power for the load power rail from the first power rail to the second power rail independently of a voltage level differential between the first voltage and the second voltage.

17. The integrated circuit of claim 12, wherein the means for switching access to power for the load power rail further includes means for preventing a short-circuit current between the first power rail and the second power rail.

18. A method for power rail multiplexing in an integrated circuit, the method comprising:

supplying power to a circuit load at a first voltage using first transistors of a first set of transistors, the first transistors coupled to a first power rail that corresponds to the first voltage, each first transistor disposed in one of multiple power-multiplexer tiles, the power-multiplexer tiles configured in a chained arrangement;

sequentially turning off the first transistors of the first set of transistors, the first transistors turned off in a first direction along the chained arrangement;

after sequentially turning off the first transistors, sequentially turning on second transistors of a second set of transistors, the second transistors coupled to a second power rail that corresponds to a second voltage, each second transistor disposed in one of the power-multiplexer tiles, the second transistors turned on in a second direction along the chained arrangement, the second direction opposite the first direction; and

supplying power to the circuit load at the second voltage using the second transistors of the second set of transistors.

20. The method of claim 18, wherein the sequentially turning off the first transistors comprises delaying a power rail selection signal that is propagating between consecutive ones of the first transistors.

21. The method of claim 18, further comprising:

controlling an operational state of a corresponding second transistor of the second set of transistors based on a voltage that controls an operational state of a corresponding first transistor of the first set of transistors.

22. The method of claim 18, wherein the sequentially turning on second transistors comprises propagating a transistor operational state feedback signal between consecutive ones of the second transistors.

23. An integrated circuit comprising:

a circuit load;

a first power rail;

a second power rail;

a load power rail that is coupled to the circuit load; and

multiple power-multiplexer tiles, each power-multiplexer tile including a first transistor coupled between the first power rail and the load power rail and a second transistor coupled between the second power rail and the load power rail,

the multiple power-multiplexer tiles disposed in a chained arrangement and configured to propagate a selection signal between consecutive power-multiplexer tiles in a first direction along the chained arrangement to disconnect the first power rail or the second power rail from the load power rail and to propagate a feedback signal between consecutive power-multiplexer tiles in a second direction along the chained arrangement to connect the second power rail or the first power rail to the load power rail, the second direction opposite the first direction.

24. The integrated circuit of claim 23, wherein:

the multiple power-multiplexer tiles are further configured to turn on the corresponding second transistor based on the first transistor having an OFF operational state and responsive to the feedback signal being indicative of an ON operational state of the consecutive second transistor.