Phase-locked loop circuit, data recovery circuit, and control method for phase-locked loop circuit

• US 9,654,115 B2
• Filed: 09/16/2016
• Issued: 05/16/2017
• Est. Priority Date: 09/16/2015
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Zhang, Bingzhao, Liu, Yongwang
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US15/268,120
• Publication Number:
  US 20170077933A1
• Time in Patent Office: 242 Days
• Field of Search: 327147-149, 327156-158
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A phase-locked loop circuit, which includes a phase frequency detector, a charge pump, a loop low-pass filter, a first voltage-current converter, a second voltage-current converter, a current-controlled oscillator, a frequency divider, a comparator, and a mode controller, where the mode controller is configured to control the switches S1, S2, and S3 included in the loop low-pass filter to connect or disconnect. Using the phase-locked loop circuit, a voltage value of a second control voltage signal VC2 provided for the first voltage-current converter can reach, in a relatively short time, a voltage value of a first control voltage signal VC1 provided for the second voltage-current converter, thereby increasing a speed of establishing the phase-locked loop circuit and implementing a quick response of the phase-locked loop circuit.

Claims

1. A phase-locked loop circuit, comprising:

a first voltage-current converter;

a second voltage-current converter;

a current-controlled oscillator;

a frequency divider;

a phase frequency detector configured to;

receive a reference source signal and a feedback signal that is output by the frequency divider; and

generate a first error signal;

a charge pump coupled to the phase frequency detector and configured to generate a first voltage signal according to the first error signal that is output by the phase frequency detector;

a loop low-pass filter, comprising a first filter, a second filter, a third node, and a fourth node, a switch (S1), a switch (S2), and a switch (S3), wherein the first filter is configured to filter out a high frequency component in the first voltage signal that is output by the charge pump and generate a first control voltage signal (VC1) to provide for the second voltage-current converter, wherein the second filter is configured to filter out the high frequency component in the first voltage signal that is output by the charge pump and generate a second control voltage signal (VC2) to provide for the first voltage-current converter, wherein the first filter comprises a first resistor (R1) and a first capacitor (C1), wherein the R1 and the C1 are connected in series, wherein the second filter comprises a second resistor (R2) and a second capacitor (C2), wherein the R2 and the C2 are connected in series, wherein the third node is a node for taking out the VC1, wherein the fourth node is another node for taking out the VC2, wherein a first end of the S1 is coupled to a first node between the R1 and the C1, wherein a second end of the S1 is coupled to a second node between the R2 and the C2, wherein two ends of the S2 are respectively coupled to the first node and the fourth node, and wherein two ends of the S3 are respectively coupled to the third node and the fourth node; and

a mode controller coupled to the loop low-pass filter and configured to control the S1 to alternatively connect and disconnect, the S2 to connect, and the S3 to disconnect in the loop low-pass filter when a bandwidth of the phase-locked loop circuit is less than a bandwidth threshold,

wherein the first voltage-current converter is coupled to the loop low-pass filter and configured to;

convert the received VC2 into a current signal; and

input the current signal to the current-controlled oscillator;

wherein the second voltage-current converter is coupled to the loop low-pass filter and configured to;

convert the received VC1 into another current signal; and

input the other current signal to the current-controlled oscillator,

wherein the current-controlled oscillator is configured to generate, according to received current signals, a phase-locked loop output signal whose frequency is a target frequency,

wherein one end of the frequency divider is coupled to the current-controlled oscillator and the other end is coupled to the phase frequency detector, and

wherein the frequency divider is configured to;

perform frequency division on the frequency of the phase-locked loop output signal that is output by the current-controlled oscillator;

set a signal that is obtained after the frequency division as a frequency division feedback signal; and

send the frequency division feedback signal to the phase frequency detector.

2. The phase-locked loop circuit according to claim 1, further comprising a comparator coupled to the first node, the second node, and the mode controller and configured to:

receive a voltage VM1 at the first node and a voltage VM2 at the second node;

determine an output signal according to a differential mode voltage between the VM1 and the VM2; and

send the output signal to the mode controller, and

wherein the mode controller is further configured to control, according to the output signal of the comparator, the S1 to alternatively connect and disconnect.

3. The phase-locked loop circuit according to claim 2, wherein the comparator is further configured to:

compare a first voltage threshold with a value of the differential mode voltage between the VM1 and the VM2; and

generate a first level signal as the output signal when the value of the differential mode voltage between the VM1 and the VM2 is greater than the first voltage threshold;

send the first level signal to the mode controller when the value of the differential mode voltage between the VM1 and the VM2 is greater than the first voltage threshold;

generate a second level signal as the output signal when the value of the differential mode voltage between the VM1 and the VM2 is not greater than the first voltage threshold; and

send the second level signal to the mode controller when the value of the differential mode voltage between the VM1 and the VM2 is not greater than the first voltage threshold, and

wherein the mode controller is further configured to;

control the S1 to connect when receiving the first level signal; and

control the S1 to disconnect when receiving the second level signal.

4. The phase-locked loop circuit according to claim 3, wherein the comparator comprises:

a selector;

a first comparator;

a common-mode voltage (VCM) generator configured to;

receive the voltage VM1 at the first node and the voltage VM2 at the second node; and

generate a VCM of the VM1 and the VM2; and

a determining component connected to the selector and the VCM generator and configured to;

compare a second voltage threshold with the VCM generated by the VCM generator;

output a first instruction signal to the selector when the VCM is less than the second voltage threshold; and

output a second instruction signal to the selector when the VCM is greater than the second voltage threshold,

wherein the selector is configured to;

receive the first instruction signal that is output by the determining component;

select to receive, according to the first instruction signal, a first output signal that is generated by the first comparator; and

set the first output signal as the output signal of the comparator, and

wherein the first comparator is configured to generate the first level signal as the first output signal when the VCM of the voltage VM1 at the first node and the voltage VM2 at the second node is less than the second voltage threshold.

5. The phase-locked loop circuit according to claim 3, wherein the comparator comprises:

a selector;

a first comparator;

a common-mode voltage (VCM) generator configured to;

receive the voltage VM1 at the first node and the voltage VM2 at the second node; and

generate a VCM of the VM1 and the VM2; and

a determining component connected to the selector and the VCM generator and configured to;

compare a second voltage threshold with the VCM generated by the VCM generator;

output a first instruction signal to the selector when the VCM is less than the second voltage threshold; and

output a second instruction signal to the selector when the VCM is greater than the second voltage threshold,

wherein the selector is configured to;

receive the first instruction signal that is output by the determining component;

select to receive, according to the first instruction signal, a first output signal that is generated by the first comparator; and

set the first output signal as the output signal of the comparator, and

wherein the first comparator is configured to generate the second level signal as the first output signal when the VCM of the voltage VM1 at the first node and the voltage VM2 at the second node is less than the second voltage threshold.

6. The phase-locked loop circuit according to claim 3, wherein the comparator comprises:

a selector;

a second comparator;

a common-mode voltage (VCM) generator configured to;

receive the voltage VM1 at the first node and the voltage VM2 at the second node; and

generate a VCM of the VM1 and the VM2; and

a determining component connected to the selector and the VCM generator and configured to;

compare a second voltage threshold with the VCM generated by the VCM generator;

output a first instruction signal to the selector when the VCM is less than the second voltage threshold; and

output a second instruction signal to the selector when the VCM is greater than the second voltage threshold,

wherein the selector is configured to;

receive the second instruction signal that is output by the determining component;

select to receive, according to the second instruction signal, a second output signal that is generated by the second comparator; and

set the second output signal as the output signal of the comparator, and

wherein the second comparator is configured to generate the first level signal as the second output signal when the VCM of the voltage VM1 at the first node and the voltage VM2 at the second node is greater than the second voltage threshold.

7. The phase-locked loop circuit according to claim 3, wherein the comparator comprises:

a selector;

a first comparator;

a common-mode voltage (VCM) generator configured to;

receive the voltage VM1 at the first node and the voltage VM2 at the second node; and

generate a VCM of the VM1 and the VM2; and

a determining component connected to the selector and the VCM generator and configured to;

compare a second voltage threshold with the VCM generated by the VCM generator;

output a first instruction signal to the selector when the VCM is less than the second voltage threshold; and

output a second instruction signal to the selector when the VCM is greater than the second voltage threshold,

wherein the selector is configured to;

receive the second instruction signal that is output by the determining component;

select to receive, according to the second instruction signal, a second output signal that is generated by the second comparator; and

set the second output signal as the output signal of the comparator, and

wherein the second comparator is configured to generate the second level signal as the second output signal when the VCM of the voltage VM1 at the first node and the voltage VM2 at the second node is greater than the second voltage threshold.

8. The phase-locked loop circuit according to claim 4, wherein the first comparator comprises:

an n-channel metal oxide semiconductor (NMOS) output stage; and

a p-channel metal oxide semiconductor (PMOS) transconductance input stage configured to;

convert each of the voltage VM1 at the first node and the voltage VM2 at the second node into a current signal to obtain two current signals; and

send the two current signals to the NMOS output stage, and

wherein the NMOS output stage is configured to;

convert each of the two received current signals into a voltage signal to obtain two voltage signals;

compare the first voltage threshold with the value of the differential mode voltage between the two voltage signals;

generate the first level signal as the first output signal when the value of the differential mode voltage between the two voltage signals is greater than the first voltage threshold; and

generate the second level signal as the first output signal when the value of the differential mode voltage between the two voltage signals is not greater than the first voltage threshold.

9. The phase-locked loop circuit according to claim 6, wherein the second comparator comprises:

a p-channel metal oxide semiconductor (PMOS) output stage; and

an n-channel metal oxide semiconductor (NMOS) transconductance input stage configured to;

convert each of the voltage VM1 at the first node and the voltage VM2 at the second node into a current signal to obtain two current signals; and

send the two current signals obtained after the conversion to a p-channel metal oxide semiconductor (PMOS) output stage, and

wherein the PMOS output stage is configured to;

convert each of the two received current signals into a voltage signal to obtain two voltage signals;

compare the first voltage threshold with the value of the differential mode voltage between the two voltage signals;

generate the first level signal as the second output signal when the value of the differential mode voltage between the two voltage signals is greater than the first voltage threshold; and

generate the second level signal as the second output signal when the value of the differential mode voltage between the two voltage signals is not greater than the first voltage threshold.

10. The phase-locked loop circuit according to claim 1, wherein the mode controller is further configured to control the S1 to connect, the S2 to disconnect, and the S3 to connect in the loop low-pass filter when the bandwidth of the phase-locked loop circuit is not less than the bandwidth threshold.

11. The phase-locked loop circuit according to claim 1, wherein the first voltage-current converter comprises a first metal oxide semiconductor (MOS) transistor, wherein the second voltage-current converter comprises a second MOS transistor, wherein the second MOS transistor is smaller than the first MOS transistor in size, wherein a gate of the second MOS transistor receives an input voltage (VC1), wherein a source of the second MOS transistor is connected to the current-controlled oscillator, wherein a drain of the second MOS transistor is connected to a power supply voltage, wherein a gate of the first MOS transistor receives an input voltage (VC2), wherein a source of the first MOS transistor is connected to the current-controlled oscillator, and wherein a drain of the first MOS transistor is connected to the power supply voltage.

12. The phase-locked loop circuit according to claim 1, further comprising a transconductance-element low-pass filter configured to filter high-frequency noise in a power supply voltage, wherein the first voltage-current converter comprises:

a first metal oxide semiconductor (MOS) transistor; and

a third MOS transistor,

wherein the second voltage-current converter comprises;

a second MOS transistor; and

a fourth MOS transistor,

wherein the second MOS transistor is smaller than the first MOS transistor in size,

wherein the fourth MOS transistor is smaller than the third MOS transistor in size,

wherein a gate of the second MOS transistor receives an input voltage (VC1),

wherein a source of the second MOS transistor is connected to the current-controlled oscillator,

wherein a drain of the second MOS transistor is connected to a source of the fourth MOS transistor,

wherein a gate of the fourth MOS transistor is connected to the transconductance-element low-pass filter,

wherein the source of the fourth MOS transistor is connected to the drain of the second MOS transistor,

wherein a drain of the fourth MOS transistor is connected to the power supply voltage,

wherein a gate of the first MOS transistor receives an input voltage (VC2),

wherein a source of the first MOS transistor is connected to the current-controlled oscillator,

wherein a drain of the first MOS transistor is connected to a source of the third MOS transistor,

wherein a gate of the third MOS transistor is connected to the transconductance-element low-pass filter,

wherein the source of the third MOS transistor is connected to the drain of the first MOS transistor, and

wherein a drain of the third MOS transistor is connected to the power supply voltage.

13. The phase-locked loop circuit according to claim 12, wherein the transconductance-element low-pass filter comprises a resistor (Rs1) and a capacitor (Cs1), wherein a first end of the Rs1 is connected to the power supply voltage, and wherein a second end of the Rs1 is connected to the Cs1.

14. The phase-locked loop circuit according to claim 1, wherein a time constant of a circuit that comprises the R1 and the C1 in the first filter is greater than a time constant of a circuit that comprises the R2 and the C2 in the second filter.

15. A data recovery circuit, comprising:

a first voltage-current converter;

a second voltage-current converter;

a current-controlled oscillator;

a frequency divider;

a phase-locked loop circuit;

a frequency detector;

a phase detector; and

a data selector,

wherein the phase-locked loop circuit comprises;

a phase frequency detector configured to;

receive a reference source signal and a feedback signal that is output by the frequency divider; and

generate a first error signal;

a charge pump coupled to the phase frequency detector and configured to generate a first voltage signal according to the first error signal that is output by the phase frequency detector;

a loop low-pass filter, comprising a first filter, a second filter, a third node, a fourth node, a switch (S1), a switch (S2), and a switch (S3), wherein the first filter is configured to filter out a high frequency component in the first voltage signal that is output by the charge pump and generate a first control voltage signal (VC1) to provide for the second voltage-current converter, wherein the second filter is configured to filter out the high frequency component in the first voltage signal that is output by the charge pump and generate a second control voltage signal (VC2) to provide for the first voltage-current converter, wherein the first filter comprises a first resistor (R1) and a first capacitor (C1), wherein the R1 and the C1 are connected in series, wherein the second filter comprises a second resistor (R2) and a second capacitor (C2), wherein the R2 and the C2 are connected in series, wherein the third node is a node for taking out the first control voltage signal (VC1), wherein the fourth node is another node for taking out the second control voltage signal (VC2), wherein a first end of the S1 is coupled to a first node between the R1 and the C1, wherein a second end of the S1 is coupled to a second node between the R2 and the C2, wherein two ends of the S2 are respectively coupled to the first node and the fourth node, and wherein two ends of the S3 are respectively coupled to the third node and the fourth node; and

a mode controller coupled to the loop low-pass filter and configured to control the S1 to alternatively connect and disconnect, the S2 to connect, and the S3 to disconnect in

the loop low-pass filter when a bandwidth of the phase-locked loop circuit is less than a bandwidth threshold,

wherein the first voltage-current converter is coupled to the loop low-pass filter and configured to;

convert the received second control voltage signal VC2 into a current signal; and

input the current signal to the current-controlled oscillator;

wherein the second voltage-current converter is coupled to the loop low-pass filter and configured to;

convert the received first control voltage signal VC1 into another current signal; and

input the other current signal to the current-controlled oscillator,

wherein the current-controlled oscillator is configured to generate, according to received current signals, a phase-locked loop output signal whose frequency is a target frequency,

wherein one end of the frequency divider is coupled to the current-controlled oscillator and the other end is coupled to the phase frequency detector,

wherein the frequency divider is configured to;

perform frequency division on the frequency of the phase-locked loop output signal that is output by the current-controlled oscillator;

set a signal that is obtained after the frequency division as a frequency division feedback signal; and

send the frequency division feedback signal to the phase frequency detector, wherein the frequency detector is coupled to the data selector and configured to;

detect whether frequencies of the reference source signal and the feedback signal in the phase-locked loop circuit are consistent;

output a first control instruction to the data selector when the frequencies are inconsistent; and

output a second control instruction to the data selector when the frequencies are consistent,

wherein the data selector is coupled to the phase detector, the frequency detector, the phase frequency detector, and the charge pump and configured to;

select to connect the phase frequency detector and the charge pump according to the first control instruction that is output by the frequency detector;

or

select to connect the phase detector and the charge pump according to the second control instruction that is output by the frequency detector,

wherein the phase detector is coupled to the data selector and the current-controlled oscillator and configured to;

compare a received link data signal with a first feedback signal that is output by the current-controlled oscillator when the phase-locked loop circuit is locked;

generate a second error signal; and

recover a data signal in the link data signal according to a second feedback signal that is output by the current-controlled oscillator when the link data signal is locked by the current-controlled oscillator, and

wherein the second error signal comprises a phase error between the link data signal and the first feedback signal.

16. A control method for a phase-locked loop circuit, comprising:

generating a first control voltage signal VC1 to provide for a second voltage-current converter in the phase-locked loop circuit;

generating a second control voltage signal VC2 to provide for a first voltage-current converter in the phase-locked loop circuit; and

controlling a S1 to alternatively connect and disconnect, a S2 to connect, and a S3 to disconnect in a loop low-pass filter in the phase-locked loop circuit when a bandwidth of the phase-locked loop circuit is less than a bandwidth threshold,

wherein the loop low-pass filter comprises a first filter, a second filter, a third node, a fourth node, the S1, the S2, and the S3,

wherein the first filter comprises a first resistor (R1) and a first capacitor (C1),

wherein the R1 and the C1 are connected in series,

wherein the second filter comprises a second resistor (R2) and a second capacitor (C2),

wherein the R2 and the C2 are connected in series,

wherein the third node is a node for taking out the VC1,

wherein the fourth node is another node for taking out the VC2,

wherein a first end of the S1 is coupled to a first node between the R1 and the C1,

wherein a second end of the S1 is coupled to a second node between the R2 and the C2,

wherein two ends of the S2 are respectively coupled to the first node and the fourth node, and

wherein two ends of the S3 are respectively coupled to the third node and the fourth node.

17. The control method according to claim 16, wherein controlling the S1 to alternatively connect and disconnect comprises:

comparing a first voltage threshold with a value of a differential mode voltage between a voltage VM1 at the first node and a voltage VM2 at the second node;

controlling the S1 to connect when the value of the differential mode voltage between the VM1 and the VM2 is greater than the first voltage threshold; and

controlling the S1 to disconnect when the value of the differential mode voltage between the VM1 and the VM2 is not greater than the first voltage threshold.

18. The control method according to claim 16, further comprising controlling the S1 to connect, the S2 to disconnect, and the S3 to connect in the loop low-pass filter when the bandwidth of the phase-locked loop circuit is not less than the bandwidth threshold.