Calibration method and apparatus for phase locked loop circuit
First Claim
1. An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, the integrated circuit device comprising:
- a calibration circuit coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator, the calibration circuit including;
a counting circuit operable for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal; and
a selection block operable for performing a convergence test using the counted number of fast clock cycles, N, and M, wherein the selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band.
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Accused Products
Abstract
An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, includes a calibration circuit. The calibration circuit is coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator. The calibration circuit includes a counting circuit for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal. The calibration circuit also includes a selection block for performing a convergence test using the counted number of fast clock cycles, N, and M. The selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band.
135 Citations
21 Claims
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1. An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, the integrated circuit device comprising:
a calibration circuit coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator, the calibration circuit including; a counting circuit operable for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal; and a selection block operable for performing a convergence test using the counted number of fast clock cycles, N, and M, wherein the selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a first divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, the method comprising:
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coupling a calibration circuit to the reference clock signal input, the input of the variable frequency oscillator and to the output of the variable frequency oscillator; selecting a frequency band of a plurality of frequency bands as a candidate calibration frequency band; counting the number of cycles of the fast clock signal over a period of time defined by a number of the reference clock cycles (M); and performing a convergence test using the counted number of fast clock cycles, N, and M; selecting another frequency band of the plurality of frequency bands as the candidate calibration frequency band in accordance with the results of the convergence test; and continuing the counting, the performing and the selecting another frequency band for a plurality of iterations to identify a last candidate calibration frequency band for the phase locked loop circuit. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, a first divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, and a second divider configured to divide the fast clock signal by a divisor (K) wherein K≠
- N, the integrated circuit device comprising;
a calibration circuit coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator, the calibration circuit including; a counting circuit operable for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal; and a selection block operable for performing a convergence test using the counted number of fast clock cycles, N, and M, wherein the selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band. - View Dependent Claims (16, 17, 18, 19, 20, 21)
- N, the integrated circuit device comprising;
Specification
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- Resources
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Current AssigneeIntegrated Device Technology Incorporated (Renesas Electronics Corporation)
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Original AssigneeIntegrated Device Technology Incorporated (Renesas Electronics Corporation)
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InventorsChu, Min
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Primary Examiner(s)Tra, Quan
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Application NumberUS15/169,997Time in Patent Office349 DaysField of Search327147-161US Class CurrentCPC Class CodesH03L 2207/06 Phase locked loops with a c...H03L 2207/50 All digital phase-locked loopH03L 7/099 concerning mainly the contr...H03L 7/0992 comprising a counter or a f...
