Alignment testing for tiered semiconductor structure

• US 9,658,281 B2
• Filed: 10/25/2013
• Issued: 05/23/2017
• Est. Priority Date: 10/25/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Mill-Jer, Peng, Ching-Nen, Lee, Mincent, Lin, Hung-Chih, Chen, Hao
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): YODICHKAS, KHRISTOPHER J
• Application Number:
  US14/063,414
• Publication Number:
  US 20150115986A1
• Time in Patent Office: 1,306 Days
• Field of Search: 3247503
• CPC Class Codes: G01B 2210/56 Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth
• CPC Class Codes: G01B 7/12 for measuring diameters
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2891 related to sensing or controlling of force, position, temperature G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G01R 31/54 Testing for continuity
• CPC Class Codes: G01R 31/66 Testing of connections, e.g. of plugs or non-disconnectable joints testing for incorrect line connections G01R31/55

Abstract

Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.

Claims

1. A method for evaluating a tiered semiconductor structure, comprising:

evaluating connectivity between a first set of vias within a first layer of a tiered semiconductor structure and spaced apart by a first pitch and a second set of vias within a second layer of the tiered semiconductor structure and spaced apart by a second pitch different than the first pitch to determine a via connection count corresponding to a number of vias within the first set of vias that contact vias within the second set of vias;

determining a via diameter for vias of the first set of vias based upon the via connection count;

determining a first offset based upon an offset measurement between a target design via and a measured center via, the first offset comprising;

an offset distance determined based upon a number of vias between the target design via and the measured center via and a pitch difference between the first pitch and the second pitch, and

an offset direction;

evaluating the tiered semiconductor structure for misalignment based upon the via diameter and the first offset; and

invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

2. The method of claim 1:

the measured center via corresponding to a middle via of a row of vias within the first set of vias that contact vias within the second set of vias, and

the target design via corresponding to an intended center via of a row of vias within the first set of vias that are designed to contact vias within the second set of vias.

3. The method of claim 1, comprising:

evaluating connectivity within a conductive arc comprising a notch with a notch angle, the conductive arc within at least one of the first layer or the second layer and a third set of vias within another of the first layer or the second layer;

responsive to determining that a first via of the third set of vias has connectivity through the conductive arc to a third via of the third set of vias and that the first via does not have connectivity to a second via of the third set of vias positioned between the first via and the third via, determining an alignment rotation having a rotational value less than the notch angle; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

4. The method of claim 1, comprising:

evaluating connectivity within a conductive arc comprising a notch with a notch angle, the conductive arc within at least one of the first layer or the second layer and a third set of vias within another of the first layer or the second layer;

responsive to determining that a first via of the third set of vias has connectivity through the conductive arc to a second via of the third set of vias adjacent to the first via and that the first via does not have connectivity to a third via of the third set of vias adjacent to the second via, determining an alignment rotation having a counterclockwise rotation value between half the notch angle and the notch angle; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

5. The method of claim 1, comprising:

evaluating connectivity within a conductive arc comprising a notch with a notch angle, the conductive arc within at least one of the first layer or the second layer and a third set of vias within another of the first layer or the second layer;

responsive to determining that a third via of the third set of vias has connectivity through the conductive arc to a second via of the third set of vias adjacent to the third via and that a first via of the third set of vias does not have connectivity to the third via, determining an alignment rotation having a clockwise rotation value between half the notch angle and the notch angle; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

6. The method of claim 1, comprising:

evaluating connectivity within a conductive arc comprising a notch with a notch angle, the conductive arc within at least one of the first layer or the second layer and a third set of vias within another of the first layer or the second layer;

responsive to determining that the conductive arc provides connectivity between a first via of the third set of vias, a second via of the third set of vias, and a third via of the third set of vias, determining an alignment rotation having a rotation value greater than the notch angle; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

7. The method of claim 1, comprising identifying the measured center via based upon the evaluating.

8. The method of claim 1, comprising:

evaluating the tiered semiconductor structure for misalignment during a CMOS stacking process of one or more tiers of the tiered semiconductor structure.

9. The method of claim 1, comprising:

transmitting a testing signal to perform a connectivity test, during which the evaluating is performed, utilizing at least one of a contact probe, a contactless coupling, or a probe coupling hybrid, the testing signal transmitted from a source separated from a test structure.

10. The method of claim 1, comprising:

transmitting a testing signal utilizing at least one of;

a direct testing signal from automatic test equipment (ATE);

or

a testing trigger created by a built in self testing engine (BIST) employed by the ATE.

11. A method for evaluating a tiered semiconductor structure, comprising:

evaluating connectivity between a first set of vias within a first layer of a tiered semiconductor structure and spaced apart by a first pitch and a second set of vias within a second layer of the tiered semiconductor structure and spaced apart by a second pitch different than the first pitch;

identifying a measured center via based upon the evaluating;

determining an offset based upon a number of vias between a target design via and the measured center via and based upon a pitch difference between the first pitch and the second pitch;

evaluating the tiered semiconductor structure for misalignment based upon the offset; and

invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

12. The method of claim 11, comprising:

evaluating connectivity within a conductive arc comprising a notch with a notch angle, the conductive arc within at least one of the first layer or the second layer and a third set of vias within another of the first layer or the second layer;

responsive to determining that the conductive arc provides connectivity between a first via of the third set of vias, a second via of the third set of vias, and a third via of the third set of vias, determining an alignment rotation having a rotation value greater than the notch angle; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

13. The method of claim 11, comprising:

evaluating connectivity within a conductive arc comprising a notch with a notch angle, the conductive arc within at least one of the first layer or the second layer and a third set of vias within another of the first layer or the second layer;

responsive to determining that a first via of the third set of vias has connectivity through the conductive arc to a third via of the third set of vias and that the first via does not have connectivity to a second via of the third set of vias positioned between the first via and the third via, determining an alignment rotation having a rotational value less than the notch angle; and

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation.

14. The method of claim 11, the evaluating comprising determining a via connection count corresponding to a number of via connections that pass a connectivity test.

15. The method of claim 14, comprising:

determining a via diameter based upon the via connection count and based upon the pitch difference.

19. The method of claim 11, the measured center via corresponding to a middle via of a row of vias within the first set of vias that contact vias within the second set of vias.

20. The method of claim 19, the target design via corresponding to an intended center via of a row of vias within the first set of vias that are designed to contact vias within the second set of vias.

16. A method for evaluating a tiered semiconductor structure, comprising:

evaluating connectivity between a first set of vias within a first layer of a tiered semiconductor structure and spaced apart by a first pitch and a second set of vias within a second layer of the tiered semiconductor structure and spaced apart by a second pitch different than the first pitch to determine a via connection count corresponding to a number of vias within the first set of vias that contact vias within the second set of vias;

determining a via diameter for vias of the first set of vias based upon the via connection count;

identifying a measured center via based upon the evaluating;

determining an offset based upon a number of vias between a target design via and the measured center via and based upon a pitch difference between the first pitch and the second pitch;

evaluating the tiered semiconductor structure for misalignment based upon the via diameter and the offset; and

invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

17. The method of claim 16:

the measured center via corresponding to a middle via of a row of vias within the first set of vias that contact vias within the second set of vias, and

the target design via corresponding to an intended center via of a row of vias within the first set of vias that are designed to contact vias within the second set of vias.

18. The method of claim 16, the via diameter further based upon the pitch difference.