Sending messages in a network-on-chip and providing a low power state for processing cores

• US 9,658,676 B1
• Filed: 02/19/2015
• Issued: 05/23/2017
• Est. Priority Date: 02/19/2015
• Status: Expired due to Fees

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Suresh, Maya, Witek, Richard Thomas, Li, Long
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Poudel, Santosh R
• Application Number:
  US14/626,716
• Time in Patent Office: 824 Days
• Field of Search: 713323, 713320
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 5/14 for overflow or underflow handling, e.g. full or empty flags
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Subject matter disclosed herein relates to arrangements and techniques for sending messages directly among processing cores and directly among co-processors over a network-on-chip (NoC). More particularly, the present disclosure provides an Application Specific Integrated Circuit (ASIC) that includes processing cores coupled together with a NoC. Each processing core and co-processor includes two corresponding buffers. A first buffer is for sending messages and a second buffer is for receiving messages. Messages are sent from a processing core directly to another processing core through the NoC. Messages are also sent from a co-processor directly to another co-processor through the NoC.

Claims

1. An Application Specific Integrated Circuit (ASIC) including:

a first processing core, wherein the first processing core includes a first send first-in first-out (FIFO) buffer configured to send messages to be sent by the first processing core and a first receive FIFO buffer configured to receive messages from other processing cores;

a second processing core, wherein the second processing core includes a second send FIFO buffer configured to send messages to be sent by the second processing core and a second receive FIFO buffer configured to receive messages from other processing cores;

a third processing core, wherein the third processing core includes a third send FIFO buffer configured to send messages to be sent by the third processing core and a third receive FIFO buffer configured to receive messages from other processing cores;

a fourth processing core, wherein the fourth processing core includes a fourth send FIFO buffer configured to send messages to be sent by the fourth processing core and a fourth receive FIFO buffer configured to receive messages from other processing cores;

memory; and

a network-on-chip (NoC) coupled to the first, second, third and fourth processing cores, wherein the processing cores are configured to send messages directly to other processing cores via the NoC bypassing the memory and to receive messages directly from the other processing cores via the NoC bypassing the memory,

wherein at least the first processing core is configured such that when a message that includes a flag that indicates a WAIT function is to be sent by the first processing core to one of (i) a second processing core of the plurality of processing cores or (ii) the memory, and the first FIFO buffer of the first processing core is full, the first processing core enters a low power state.

2. The ASIC of claim 1, wherein at least the first processing core is configured to enter a low power state when the first send FIFO buffer of the first processing core is full.

3. The ASIC of claim 1 wherein at least the first processing core is configured to enter a low power state when the first receive FIFO buffer of the first processing core is empty.

4. The ASIC of claim 1, wherein each of the first, second, third and fourth send FIFO buffers and each of the first, second, third and fourth receive FIFO buffers is configured to store a maximum of four messages.

5. The ASIC of claim 1, wherein at least the first processing core is further configured such that if a controller of the NoC indicates that the second receive FIFO buffer of the second processing core is full, the first processing core enters the low power state.

6. The ASIC of claim 1, wherein the at least the first processing core is further configured to ignore a message if the first FIFO buffer is full and the message does not include a flag that indicates a WAIT function.

7. A circuit including:

a plurality of processing cores, wherein each processing core is associated with a corresponding first buffer and a corresponding second buffer;

memory; and

a network-on-chip (NoC) coupled to the plurality of processing cores, wherein the processing cores are configured to send messages directly to other processing cores via the NoC bypassing the memory and to receive messages directly from other processing cores via the NoC bypassing the memory,

wherein at least a first processing core is configured such that when a message that includes a flag that indicates a WAIT function is to be sent by the first processing core to one of (i) a second processing core of the plurality of processing cores or (ii) the memory and the first buffer of the first processing core is full, the first processing core enters a low power state.

8. The circuit of claim 7, wherein each first buffer and each second buffer is configured to store a maximum of four messages.

9. The circuit of claim 7, wherein the plurality of processing cores comprises four processing cores.

10. The circuit of claim 7, wherein at least a first processing core of the plurality of processing cores is configured to enter a low power state when the corresponding first buffer of the first processing core is full.

11. The circuit of claim 10 wherein at least the first processing core is further configured such that after the first processing core enters the low power state, the first processing core remains in the low power state until a first buffer of the first processing core is no longer full.

12. The circuit of claim 10, wherein entering the low power state comprises deactivating a clock of the first processing core, wherein the first clock comprises one or more of a clock for instruction fetching, a clock for instruction decoding, a clock for instruction execution, a clock for memory writing-back, and a clock for register writing-back.

13. The circuit of claim 12, wherein a second clock of the processing core that is not deactivated is used to one or more of (i) send and receive messages, (ii) handle traffic to and from memory, and (iii) handle interrupts.

14. The circuit of claim 7, wherein at least a first processing core of the plurality of processing cores is configured to enter a low power state when the second buffer of the first processing core is empty.

15. The circuit of claim 14, wherein the first processing core is further configured such that when the first processing core enters the low power state, the first processing core remains in the low power state until the first buffer of the first processing core is no longer empty.

16. The circuit of claim 14, wherein entering the low power state comprises deactivating a clock of the first processing core, wherein the first clock comprises one or more of a clock for instruction fetching, a clock for instruction decoding, a clock for instruction execution, a clock for memory writing-back, and a clock for register writing-back.

17. The circuit of claim 16, wherein a second clock of the first processing core that is not deactivated is used to one or more of (i) send and receive messages, (ii) handle traffic to and from memory, and (iii) handle interrupts.

18. The circuit of claim 7, wherein at least the first processing core is further configured such that if a controller of the NoC indicates that the second receive FIFO buffer of the second processing core is full, the first processing core enters the low power state.

19. The circuit of claim 7, wherein the at least the first processing core is further configured to ignore a message if the first buffer is full and the message does not include a flag that indicates a WAIT function.

20. A method of sending messages among a plurality of processing nodes via a network-on-chip (NoC), wherein the plurality of processing nodes and NoC are included within an ASIC, the method comprising:

moving a message to send to a first buffer of a first processing node; and

sending the message from the first buffer of the first processing node directly to a second buffer of a second processing node through the NoC bypassing memory,

wherein the first processing core is configured such that when the message to send includes a flag that indicates a WAIT function and the first buffer is full, the first processing node enters a low power state.

21. The method of claim 20, further comprising if the second buffer is full, holding the message in the first buffer and activating, by the first processing node, a low power state until the second buffer is not full.

22. The method of claim 21, wherein activating the low power state comprises deactivating a clock of the processing node, wherein the first clock comprises one or more of a clock for instruction fetching, a clock for instruction decoding, a clock for instruction execution, a clock for memory writing-back, and a clock for register writing-back.

23. The method of claim 22, wherein a second clock of the processing node that is not deactivated is used to one or more of (i) send and receive messages, (ii) handle traffic to and from memory, and (iii) handle interrupts.

24. The method of claim 20, further comprising if the second buffer is empty, activating, by the second processing node, a low power state until the second buffer is not empty.