Induced thermal gradients

• US 9,658,678 B2
• Filed: 12/23/2011
• Issued: 05/23/2017
• Est. Priority Date: 03/31/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shoemaker, Kenneth D.
• Primary Examiner(s): Verbitsky, Gail Kaplan
• Application Number:
  US13/336,806
• Publication Number:
  US 20120249219A1
• Time in Patent Office: 1,978 Days
• Field of Search: 374170, 374178, 374171-172, 374 1, 374137, 374 29, 374 30, 702 99, 702130, 702136, 700299, 711100
• CPC Class Codes: G01K 3/08 giving differences of values using thermoelectric elements G01K7/02; giving differentiated values
• CPC Class Codes: G01K 7/00 Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat giving results other than momentary value of temperature G01K3/00 ; Power supply therefor, e.g. using thermoelectric elements
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

Claims

1. A semiconductor device comprising:

a memory die having a dynamic random access memory (DRAM) array with a configurable self-refresh rate, a mode register including a storage location for at least one thermal offset bit, and a memory thermal sensor electrically coupled to the DRAM array;

a controller die thermally coupled with the memory die, the controller die including at least one thermal sensor to detect a thermal condition and circuitry to provide the at least one thermal offset bit to the storage location for the thermal offset bit of the mode register; and

a temperature compensated self-refresh (TCSR) circuit located on the memory die, the TCSR circuit operable to modify the self-refresh rate of the memory array responsive, at least in part, to the thermal offset bit, wherein the TCSR utilizes the thermal offset bit to determine a temperature difference between a thermal sensor location on the controller die and a thermal sensor location on the memory die.

2. The semiconductor device of claim 1 wherein the controller die comprises at least a processor core.

3. The semiconductor device of claim 1 wherein the controller die comprises a system on a chip (SoC).

4. An apparatus comprising:

a first die including a memory with a configurable self-refresh rate, a thermal sensor, and a mode register, the mode register including a storage location for one or more thermal offset bits;

a second die coupled with the first die, the second die including at least one thermal sensor to detect a thermal condition and circuitry to provide the one or more thermal offset bits to the storage location for the one or more thermal offset bits; and

a circuit located on the first die, the circuit operable to modify the self-refresh rate for the memory of the first die responsive, at least in part, to the one or more thermal offset bits, wherein the circuit is to utilize the one or more thermal offset bits to determine a temperature difference between a thermal sensor location on the second die and a thermal sensor location on the first die. Please add the following new claims;

5. The apparatus of claim 4 wherein the second die comprises at least a processor core.

6. The apparatus of claim 4 wherein the second die comprises a system on a chip (SoC).