Multi-threaded low-level startup for system boot efficiency
First Claim
1. A method for executing a plurality of startup instructions for a device, the method comprising:
- accessing, by a first processor of the device, a first startup instruction of the plurality of startup instructions using an address hard coded in the first processor, wherein accessing the first startup instruction is performed in response to a startup of the device;
executing, by the first processor, the first startup instruction of the plurality of startup instructions to perform a first task;
accessing, by a second processor of the device, a second startup instruction of the plurality of startup instructions using an address hard coded in the second processor, wherein accessing the second startup instruction is performed in response to the startup of the device; and
executing, by the second processor, the second startup instruction of the plurality of startup instructions to perform a second task, wherein at least a portion of the first task and at least a portion of the second task are performed at a same time.
1 Assignment
0 Petitions
Accused Products
Abstract
Methods, computer-readable media and devices for executing a plurality of startup instructions are disclosed. For example, a method includes a first processor of a device accessing a plurality of startup instructions in response to a startup of the device. The first processor then executes a first startup instruction of the plurality of startup instructions to perform a first task and executes a second startup instruction of the plurality of startup instructions. The executing the second startup instruction causes the first processor to send a further instruction to a second processor of the device to perform a second task. At least a portion of the first task and at least a portion of the second task are performed at a same time.
-
Citations
21 Claims
-
1. A method for executing a plurality of startup instructions for a device, the method comprising:
-
accessing, by a first processor of the device, a first startup instruction of the plurality of startup instructions using an address hard coded in the first processor, wherein accessing the first startup instruction is performed in response to a startup of the device; executing, by the first processor, the first startup instruction of the plurality of startup instructions to perform a first task; accessing, by a second processor of the device, a second startup instruction of the plurality of startup instructions using an address hard coded in the second processor, wherein accessing the second startup instruction is performed in response to the startup of the device; and executing, by the second processor, the second startup instruction of the plurality of startup instructions to perform a second task, wherein at least a portion of the first task and at least a portion of the second task are performed at a same time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A non-transitory computer-readable medium storing a plurality of startup instructions which, when executed by a first processor of a device, cause the first processor to perform operations, the operations comprising:
-
performing a first task comprising an initialization of a memory, in response to a startup of the device; and sending a further instruction to a second processor of the device to perform a second task, wherein; at least a portion of the first task and at least a portion of the second task are performed at a same time; and the second task comprises writing a programmable logic image to a programmable logic portion of the device. - View Dependent Claims (16)
-
-
17. An apparatus comprising:
-
a first processor; a second processor; and a non-transitory computer-readable medium storing a plurality of startup instructions, wherein; the first processor is configured to access a first startup instruction of the plurality of startup instructions using an address hard coded in the first processor in response to a startup of the apparatus and to execute the first startup instruction to perform a first task; the second processor is configured to access a second startup instruction of the plurality of startup instructions using an address hard coded in the second processor in response to the startup of the apparatus and to execute the second startup instruction to perform a second task; and the first processor and the second processor are configured to perform at least a portion of the first task and at least a portion of the second task at a same time. - View Dependent Claims (18, 19, 20, 21)
-
Specification