Adaptive clock throttling for event processing

• US 9,658,902 B2
• Filed: 08/22/2013
• Issued: 05/23/2017
• Est. Priority Date: 08/22/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Carey, James E., Archer, Charles J., Blocksome, Michael A., Sanders, Philip J.
• Primary Examiner(s): Butler, Dennis M
• Application Number:
  US13/973,713
• Publication Number:
  US 20150058657A1
• Time in Patent Office: 1,370 Days
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods, apparatuses, and computer program products for adaptive clock throttling for event processing are provided. Embodiments include an event processing system receiving a plurality of events from one or more components of the distributed processing system. Embodiments also include the event processing system determining that an arrival attribute of the plurality of events exceeds an arrival threshold. Embodiments also include the event processing system, adjusting, in response to determining that the arrival attribute of the plurality of events exceeds the arrival threshold, a clock speed of at least one of the event processing system and a component of the distributed processing system.

Claims

1. A method of adaptive clock throttling for event processing in a distributed processing system, the method comprising:

receiving, by an event processing system, a plurality of events from one or more components of the distributed processing system;

determining, by the event processing system, that an arrival attribute of the plurality of events exceeds an arrival threshold; and

in response to determining that the arrival attribute of the plurality of events exceeds the arrival threshold, adjusting, by the event processing system, a clock speed of at least one of the event processing system and a component of the distributed processing system, said adjusting including;

determining for each component, by the event processing system, a total number of events received from the component;

identifying, by the event processing system, any components of the distributed processing system having a total number of events that exceed a predetermined total event number threshold; and

for each of the identified components, reducing, by the event processing system, the clock speed of one or more processors of the identified component.

2. The method of claim 1 wherein adjusting, by the event processing system, a clock speed of at least one of the event processing system and a component of the distributed processing system includes:

identifying within the plurality of events, by the event processing system, events of one or more particular predetermined types;

identifying, by the event processing system, the components of the distributed processing system that produced the identified events; and

for each of the identified components, adjusting based on the particular predetermined type of the events produced by the component, by the event processing system, the clock speed of one or more processors of the identified component.

3. The method of claim 1 further comprising in response to determining that the arrival attribute of the plurality of events exceeds the arrival threshold, adjusting, by the event processing system, an event retrieval time period for one or more components of the distributed processing system.

4. The method of claim 1 wherein the arrival attribute is a component event arrival rate;

and wherein the arrival threshold is a maximum component event arrival rate threshold.

5. The method of claim 1 wherein the arrival attribute is an event analyzer arrival rate;

and wherein the arrival threshold is a maximum event analyzer arrival rate threshold.

6. An apparatus for adaptive clock throttling for event processing in a distributed processing system, the apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that when executed by the computer processor cause the apparatus to carry out the steps of:

receiving, by an event processing system, a plurality of events from one or more components of the distributed processing system;

determining, by the event processing system, that an arrival attribute of the plurality of events exceeds an arrival threshold; and

in response to determining that the arrival attribute of the plurality of events exceeds the arrival threshold, adjusting, by the event processing system, a clock speed of at least one of the event processing system and a component of the distributed processing system, said adjusting including;

identifying within the plurality of events, by the event processing system, events of one or more particular predetermined types;

identifying, by the event processing system, the components of the distributed processing system that produced the identified events; and

for each of the identified components, adjusting based on the particular predetermined type of the events produced by the component, by the event processing system, the clock speed of one or more processors of the identified component.

7. The apparatus of claim 6 wherein adjusting, by the event processing system, a clock speed of at least one of the event processing system and a component of the distributed processing system includes:

determining for each component, by the event processing system, a total number of events received from the component;

identifying, by the event processing system, any components of the distributed processing system having a total number of events that exceed a predetermined total event number threshold; and

for each of the identified components, reducing, by the event processing system, the clock speed of one or more processors of the identified component.

8. The apparatus of claim 6 further comprising computer program instructions that when executed by the computer processor cause the apparatus to carry out the steps of in response to determining that the arrival attribute of the plurality of events exceeds the arrival threshold, adjusting, by the event processing system, an event retrieval time period for one or more components of the distributed processing system.

9. The apparatus of claim 6 wherein the arrival attribute is a component event arrival rate;

and wherein the arrival threshold is a maximum component event arrival rate threshold.

10. The apparatus of claim 6 wherein the arrival attribute is an event analyzer arrival rate;

and wherein the arrival threshold is a maximum event analyzer arrival rate threshold.

11. A computer program product for adaptive clock throttling for event processing in a distributed processing system, the computer program product disposed upon a non-transitory computer readable storage medium, the computer program product comprising computer program instructions that when executed by a computer cause the computer to carry out the steps of:

receiving, by an event processing system, a plurality of events from one or more components of the distributed processing system;

determining, by the event processing system, that an arrival attribute of the plurality of events exceeds an arrival threshold; and

in response to determining that the arrival attribute of the plurality of events exceeds the arrival threshold, adjusting, by the event processing system, a clock speed of at least one of the event processing system and a component of the distributed processing system, including;

determining for each component, by the event processing system, a total number of events received from the component;

identifying, by the event processing system, any components of the distributed processing system having a total number of events that exceed a predetermined total event number threshold; and

for each of the identified components, reducing, by the event processing system, the clock speed of one or more processors of the identified component.

12. The computer program product of claim 11 wherein adjusting, by the event processing system, a clock speed of at least one of the event processing system and a component of the distributed processing system includes:

identifying within the plurality of events, by the event processing system, events of one or more particular predetermined types;

identifying, by the event processing system, the components of the distributed processing system that produced the identified events; and

for each of the identified components, adjusting based on the particular predetermined type of the events produced by the component, by the event processing system, the clock speed of one or more processors of the identified component.

13. The computer program product of claim 11 further comprising computer program instructions that when executed by a computer cause the computer to carry out the steps of in response to determining that the arrival attribute of the plurality of events exceeds the arrival threshold, adjusting, by the event processing system, an event retrieval time period for one or more components of the distributed processing system.

14. The computer program product of claim 11 wherein the arrival attribute is a component event arrival rate;

and wherein the arrival threshold is a maximum component event arrival rate threshold.

15. The computer program product of claim 11 wherein the arrival attribute is an event analyzer arrival rate;

and wherein the arrival threshold is a maximum event analyzer arrival rate threshold.