Modeling pattern dependent effects for a 3-D virtual semiconductor fabrication environment

• US 9,659,126 B2
• Filed: 01/26/2015
• Issued: 05/23/2017
• Est. Priority Date: 01/26/2014
• Status: Active Grant

• Current Assignee: Coventor, Inc. (Lam Research Corporation)
• Original Assignee: Coventor, Inc. (Lam Research Corporation)
• Inventors: Greiner, Kenneth B., Fried, David M., Faken, Daniel, Kamon, Mattan
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US14/605,523
• Publication Number:
  US 20150213176A1
• Time in Patent Office: 848 Days
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G05B 19/41885 characterised by modeling, simulation of the manufacturing system
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Improving semiconductor device fabrication by enabling the identification and modeling of pattern dependent effects of fabrication processes is discussed. In one embodiment a local mask is generated from a 3-D model of a semiconductor device structure that was created in a 3-D virtual semiconductor fabrication environment from 2-D design layout data and a fabrication process sequence. The local mask is combined with a global mask based on the original design layout data to create a combined mask. The combined mask is convolved with at least one proximity function to generate a loading map which may be used to modify the behavior of one or more processes in the process sequence. This behavior modification enables the 3-D virtual semiconductor fabrication environment to deliver more accurate 3-D models that better predict the 3-D device structure when performing the virtual semiconductor device fabrication that serves as a prelude to physical fabrication.

Claims

1. A non-transitory computer-readable medium holding computer-executable instructions for identifying and modeling pattern dependent effects in a 3-D virtual semiconductor device fabrication environment provided by a computing device, the instructions when executed causing the computing device to:

generate a 2-D local mask from a 3-D model of a semiconductor device structure;

combine a global mask corresponding to 2D design layout data with the local mask to create a combined mask;

convolve at least one proximity function with the combined mask to create at least one convolved mask;

create a loading map using the at least one convolved mask, the loading map indicative of process behavior for a pattern dependent process step for virtual semiconductor device fabrication that varies as a result of one or more of pattern density, feature size or aspect ratio dependence; and

execute an algorithm to model the pattern dependent process step during virtual semiconductor device fabrication, a behavior of the algorithm altered based on the loading map.

2. The medium of claim 1 wherein the pattern dependent process step includes a pattern dependence relation that defines the loading map and the instructions when executed further cause the computing device to:

create a loading map by using the pattern dependence relation to combine the at least one convolved mask; and

use the loading map to modify the process behavior of the pattern dependent process step by scaling one or more nominal process parameters.

3. The medium of claim 1 wherein the pattern dependent process step is an etch process.

4. The medium of claim 3 wherein the etch process is a predictive multi-etch algorithm.

5. The medium of claim 1 wherein the process behavior is an etch rate that varies based on pattern density.

6. The medium of claim 1 wherein the process behavior is an etch profile that varies based on feature size.

7. The medium of claim 1 wherein the pattern dependent process step performs chemical mechanical polishing.

8. The medium of claim 1 wherein the pattern dependent process step performs deposition.

9. The medium of claim 1 wherein the at least one proximity function is a normalized two-dimensional Gaussian function.

10. The medium of claim 1 wherein the pattern dependent process step includes a pattern dependence relation that defines the loading map and wherein the pattern dependence relation is a linear combination of up to two proximity functions expressed as:

f({right arrow over (x)})=c₀+c₁p₁(r₁)*M({right arrow over (x)})+c₂pc(r₂)*M({right arrow over (x)})

where c₀, c₁, c₂ are constant coefficients chosen by the user, r₁, r₂ are proximity function radii chosen by the user, p₁ and p₂ are proximity functions, and M is the combined mask.

11. A non-transitory computer-readable medium holding computer-executable instructions for identifying and modeling pattern dependent effects in a 3-D virtual semiconductor device fabrication environment provided by a computing device, the instructions when executed causing the computing device to:

receive 2D design layout data and a fabrication process sequence for a semiconductor device structure, the fabrication process sequence including a pattern dependent process step, the pattern dependent process step including a pattern dependence relation;

build, during a virtual fabrication run to virtually fabricate the semiconductor device structure, a 3-D model of a semiconductor device structure by executing the process sequence up until the pattern dependent process step;

generate a 2-D local mask from a 3-D model of a semiconductor device structure built by executing the process sequence up until the pattern dependent process step;

convolve at least one proximity function with the local mask to create at least one convolved local mask;

convolve at least one proximity function with a global mask based on 2D design layout data to create at least one convolved global mask;

create a loading map using the convolved local and global masks, the loading map indicative of process behavior for a pattern dependent process step for virtual semiconductor device fabrication that varies as a result of one or more of pattern density, feature size or aspect ratio dependence;

execute an algorithm to model the pattern dependent process step during virtual semiconductor device fabrication, a behavior of the algorithm altered based on the loading map; and

execute a remainder of the process sequence following the pattern dependent process step to complete the build of the 3-D model of the semiconductor device structure.

12. The medium of claim 11 wherein the instructions when executed further cause the computing device to:

create a loading map by using the pattern dependence relation to combine the at least one convolved global mask and at least one convolved local mask; and

use the loading map to modify the process behavior of the pattern dependent process step by scaling one or more nominal process parameters.

13. A computer-implemented method for identifying and modeling pattern dependent effects in a 3-D virtual semiconductor device fabrication environment, comprising:

generating a 2-D local mask from a 3-D model of a semiconductor device structure;

combining a global mask corresponding to 2D design layout data with the local mask to create a combined mask;

convolving at least one proximity function with the combined mask to create at least one convolved mask;

creating a loading map using the at least one convolved mask, the loading map indicative of process behavior for a pattern dependent process step for virtual semiconductor device fabrication that varies as a result of one or more of pattern density, feature size or aspect ratio dependence; and

executing an algorithm to model the pattern dependent process step during virtual semiconductor device fabrication, a behavior of the algorithm altered based on the loading map.

14. The method of claim 13, further comprising:

creating a loading map by using the pattern dependence relation to combine the at least one convolved mask; and

using the loading map to modify the process behavior of the pattern dependent process step by scaling one or more nominal process parameters.

15. The method of claim 13 wherein the pattern dependent process step is an etch process.

16. The method of claim 15 wherein the etch process is a predictive multi-etch algorithm.

17. The method of claim 13 wherein the process behavior is an etch rate that varies based on pattern density.

18. The method of claim 13 wherein the process behavior is an etch profile that varies based on feature size.

19. The method of claim 13 wherein the pattern dependent process step performs chemical mechanical polishing.

20. The method of claim 13 wherein the pattern dependent process step performs deposition.

21. The method of claim 13 wherein the at least one proximity function is a normalized two-dimensional Gaussian function.

22. The method of claim 13 wherein the pattern dependent process step includes a pattern dependence relation that defines the loading map and wherein the pattern dependence relation is a linear combination of up to two proximity functions expressed as:

f({right arrow over (x)})=c₀+c₁p₁(r₁)*M({right arrow over (x)})+c₂p₂(r₂)*M({right arrow over (x)})

where c₀, c₁, c₂ are constant coefficients chosen by the user, r₁, r₂ are proximity function radii chosen by the user, p₁ and p₂ are proximity functions, and M is the combined mask.

23. A computer-implemented method for identifying and modeling pattern dependent effects in a 3-D virtual semiconductor device fabrication environment, comprising:

receiving 2D design layout data and a fabrication process sequence for a semiconductor device structure, the fabrication process sequence including a pattern dependent process step, the pattern dependent process step including a pattern dependence relation;

building, during a virtual fabrication run to virtually fabricate the semiconductor device structure, a 3-D model of a semiconductor device structure by executing the process sequence up until the pattern dependent process step;

generating a 2-D local mask from a 3-D model of a semiconductor device structure built by executing the process sequence up until the pattern dependent process step;

convolving at least one proximity function with the local mask to create at least one convolved local mask;

convolving one or more proximity functions with a global mask based on 2D design layout data to create at least one convolved global mask;

creating a loading map using the convolved local and global masks, the loading map indicative of process behavior for a pattern dependent process step for virtual semiconductor device fabrication that varies as a result of one or more of pattern density, feature size or aspect ratio dependence;

executing an algorithm to model the pattern dependent process step during virtual semiconductor device fabrication, a behavior of the algorithm altered based on the loading map; and

executing a remainder of the process sequence following the pattern dependent process step to complete the build of the 3-D model of the semiconductor device structure.

24. The method of claim 23, further comprising:

creating a loading map by using the pattern dependence relation to combine the at least one convolved global mask and at least one convolved local mask; and

using the loading map to modify the process behavior of the pattern dependent process step by scaling one or more nominal process parameters.

25. A computer-implemented method for identifying and modeling pattern dependent effects in a 3-D virtual semiconductor device fabrication environment, comprising:

receiving 2D design layout data and a fabrication process sequence for a semiconductor device structure, the fabrication process sequence including a pattern dependent process step, the pattern dependent process step including a pattern dependence relation;

building, during a virtual fabrication run to virtually fabricate the semiconductor device structure, a 3-D model of a semiconductor device structure by executing the process sequence up until the pattern dependent process step;

generating a 2-D local mask from the 3-D model of a semiconductor device structure built by executing the process sequence up until the pattern dependent process step;

combining a global mask corresponding to the 2D design layout data with the local mask to create a combined mask;

convolving at least one proximity function with the combined mask to create at least one convolved mask;

creating a loading map using the at least one convolved mask, the loading map indicative of process behavior for a pattern dependent process step for virtual semiconductor device fabrication that varies as a result of one or more of pattern density, feature size or aspect ratio dependence;

executing an algorithm to model the pattern dependent process step during virtual semiconductor device fabrication, a behavior of algorithm altered based on the loading map; and

executing a remainder of the process sequence following the pattern dependent process step to complete the build of the 3-D model of the semiconductor device structure.

26. The method of claim 25, further comprising:

creating a loading map by using the pattern dependence relation to combine the at least one convolved mask; and

using the loading map to modify the process behavior of the pattern dependent process step by scaling one or more nominal process parameters.

27. A non-transitory computer-readable medium holding computer-executable instructions for identifying and modeling pattern dependent effects in a 3-D virtual semiconductor device fabrication environment provided by a computing device, the instructions when executed causing the computing device to:

receive 2D design layout data and a fabrication process sequence for a semiconductor device structure, the fabrication process sequence including a pattern dependent process step, the pattern dependent process step including a pattern dependence relation;

build, during a virtual fabrication run to virtually fabricate the semiconductor device structure, a 3-D model of a semiconductor device structure by executing the process sequence up until the pattern dependent process step;

generate a 2-D local mask from the 3-D model of a semiconductor device structure built by executing the process sequence up until the pattern dependent process step;

combine a global mask corresponding to the 2D design layout data with the local mask to create a combined mask;

convolve at least one proximity function with the combined mask at least one convolved mask;

create a loading map using the at least one convolved mask, the loading map indicative of process behavior for a pattern dependent process step for virtual semiconductor device fabrication that varies as a result of one or more of pattern density, feature size or aspect ratio dependence;

execute an algorithm to model the pattern dependent process step during virtual semiconductor device fabrication, a behavior of the algorithm altered based on the loading map; and

execute a remainder of the process sequence following the pattern dependent process step to complete the build of the 3-D model of the semiconductor device structure.

28. The medium of claim 27 wherein the instructions when executed further cause the computing device to:

create a loading map by using the pattern dependence relation to combine the at least one convolved mask; and

use the loading map to modify the process behavior of the pattern dependent process step by scaling one or more nominal process parameters.