Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem

• US 9,659,340 B2
• Filed: 06/16/2014
• Issued: 05/23/2017
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Lucidlogix Technologies Ltd. (Alphabet Inc.)
• Inventors: Remez, Offir, Sela, Guy, Shoshan, Yoel
• Primary Examiner(s): NGUYEN, HAU H
• Application Number:
  US14/304,991
• Publication Number:
  US 20140292775A1
• Time in Patent Office: 1,072 Days
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A graphics processing chip includes multiple graphics pipeline cores and multi-pipeline core logic circuitry to process graphic data streams received from a processor and to drive multiple GPUs on the multiple graphics pipeline cores.

Claims

1. A multi-graphics command processor chip for use within a computing system, said multi-graphics command processor chip comprising:

multiple graphics command processor driven pipeline cores wherein each said graphics command driven pipeline core includes a graphics command processor and generates pixel values of images associated with at least a portion of a digital image to be displayed on said display surface;

a routing center for distributing graphics data received from one or more computer command processors to said multiple graphics command processor driven pipeline cores and for collecting rendering results from said multiple graphics command and processor driven pipeline cores; and

,

a display interface for receiving said rendering results from said routing center wherein said multiple graphics command processor pipeline cores, said routing center, said processing element, and said display interface are implemented on a single semiconductor chip and wherein said multiple graphics command processor pipeline cores are arranged to work in parallel on said single semiconductor chip to receive graphics data from said routing center according to a parallelization mode, wherein the parallelization mode is selected from one of;

(a) an object division mode;

or (b) an object division mode and a time division mode;

or (c) an object division mode and a time division mode and an image division mode; and

wherein said command processor chip additionally comprises an auxiliary memory for storing data and wherein the stored data comprises intermediate processing results from one or more of said multiple graphics command processor driver pipeline cores, composition data and processed data for display.

2. The graphics processing chip according to claim 1 wherein the chip is a silicon chip.

3. The graphics processing chip according to claim 1 wherein the chip comprises a low power chip.

4. The graphic processing chip according to claim 1 wherein the chip is of monolithic construction.

5. The graphic processing chip according to claim 1 wherein said multi-graphics command processor chip comprises a control unit to control the distribution of said graphics data according to the selected parallelization mode.

6. The graphic processing chip according to claim 1 wherein said multi-graphics command processor chip comprises a compositing unit to compose a fully rendered frame from a plurality of partially rendered frames.

7. The graphic processing chip according to claim 1 wherein said multi-graphics command processor chip comprises a profiling unit to determine which parailelization mode is to be used to render said graphics data.

8. The graphics processing chip according to claim 1 wherein the display interface drives one or more display screens.

9. The graphics processing chip according to claim 1 wherein the auxiliary memory comprises a cache.