Apparatuses and methods for performing corner turn operations using sensing circuitry

• US 9,659,605 B1
• Filed: 04/20/2016
• Issued: 05/23/2017
• Est. Priority Date: 04/20/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tiwari, Sanjay, Zawodny, Jason T.
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US15/133,861
• Time in Patent Office: 398 Days
• Field of Search: 365 63, 36518905, 36518503, 36518521, 36518525, 36518518, 365203, 365204, 36523003, 36523006
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1036 using data shift registers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. The example apparatus comprises a controller configured to cause a corner turn operation using sensing circuitry on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells.

Claims

1. An apparatus comprising:

a first group of memory cells coupled to an access line and a plurality of sense lines;

a second group of memory cells coupled to a plurality of access lines and a sense line, wherein the access line is a different access line than each of the plurality of access lines; and

a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

2. The apparatus of claim 1, wherein the controller is further configured to operate the first and second group of memory cells and the sensing circuitry to perform a number of AND operations and SHIFT operations without performing a sense line address access.

3. The apparatus of claim 2, wherein the sensing circuitry comprises a number of transistors on pitch with a number of memory cells of a number of columns of complementary sense lines corresponding to the first and second groups of memory cells.

4. The apparatus of claim 3, wherein the sensing circuitry comprises a sense amplifier and a compute component corresponding to each respective one of the number of columns.

5. The apparatus of claim 4, wherein the sense amplifier further comprises a primary latch and the compute component comprises a secondary latch.

6. A method for performing a corner turn, comprising:

performing, in parallel, a plurality of corner turn operations on an element stored in a number of first memory cells coupled to a first access line and to a number of sense lines of a memory array,

wherein a result of performing the plurality of corner turn operations comprises the element being stored in a number of second memory cells coupled to a plurality of access lines different than the first access line and a sense line of the number of sense lines.

7. The method of claim 6, wherein a number of the plurality of corner turn operations performed corresponds to a width of the elements independent of a number of the elements.

8. The method of claim 6, wherein a first data unit of the element is:

initially stored in a memory cell coupled to the access line and to a first of the number of sense lines; and

subsequent to performance of the plurality of corner turn operations, stored in a memory cell coupled to an access line of the plurality of access lines and the first sense line.

9. The method of claim 8, wherein additional data units of the element are:

initially stored in memory cells coupled to the access line and to sense lines of the number of sense lines other than the first sense line; and

subsequent to performance of the plurality of corner turn operations, stored in memory cells coupled to the number of access lines and the first sense line.

10. The method of claim 6, wherein a first data unit of the element is:

initially stored in a memory cell coupled to the access line and to a first of the number of sense lines; and

subsequent to performance of the plurality of corner turn operations, stored in a memory cell coupled to an access line of the plurality of access lines and a second sense line of the number of sense lines.

11. The method of claim 10, wherein:

the first data unit is a most significant bit and a second data unit is a second most significant bit;

the second data unit is initially stored in a memory cell coupled to the access line and to a second of the number of sense lines; and

subsequent to performance of the plurality of corner turn operations, the first data unit, the second data unit, and additional data units are stored in memory cells coupled to the number of access lines and the second sense line.

12. The method of claim 6, wherein the element includes:

a first data unit is initially stored in a memory cell coupled to the first access line and a first sense line;

a second data unit is initially stored in a memory cell coupled to the first access line and a second sense line;

a third data unit is initially stored in a memory cell coupled to the first access line and a third sense line; and

subsequent to performing the number of corner turn operations, the first data unit is stored in a memory cell coupled to an access line other than the first access line and a sense line other than the first sense line.

13. The method of claim 12, wherein the first access line, the second access line, and the third access line are different access lines and are successively ordered next to each other.

14. A method for performing a corner turn, comprising:

performing a plurality of corner turn operations on elements stored in a number of first memory cells coupled to a first access line and to a number of sense lines of a memory array,

wherein;

a result of performing the plurality of corner turn operations comprises each of the elements being stored in a number of second memory cells coupled to a plurality of access lines and a sense line of the number of sense lines;

the first access line is a different access line than each of the plurality of access lines; and

a controller controls sensing circuitry to perform the plurality of corner turn operations in parallel on each of the elements.

15. The method of claim 14, wherein performing the plurality of corner turn operations comprises relocating, in parallel, a first data unit of each of the elements from being stored in memory cells coupled to the first access line to being stored in memory cells coupled to a second access line of the plurality of access lines.

16. The method of claim 15, wherein performing the plurality of corner turn operations comprises relocating, in parallel, a second data unit of each of the elements from being stored in memory cells coupled to the first access line to being stored in memory cells coupled to a third access line of the plurality of access lines.

17. The method of claim 16, wherein performing the plurality of corner turn operations comprises relocating, in parallel, a respective third data unit and fourth data unit of each of the elements stored in memory cells coupled to the first access line to being stored in memory cells coupled to a fourth access line and fifth access line, respectively, of the plurality of access lines.

18. The method of claim 14, wherein a number of the plurality of corner turn operations performed corresponds to a width of the elements independent of a number of the elements.

19. The method of claim 14, wherein which of the plurality of sense lines each of the elements is stored in is indicated by a particular skip value.

20. The method of claim 19, wherein the particular skip value indicates a particular number of SHIFT operations to perform.

21. The method of claim 19, wherein:

when the particular skip value is one, a first of the elements is stored in memory cells coupled to a consecutively second sense line; and

when the particular skip value is two, the first of the elements is stored in memory cells coupled to a consecutively third sense line.

22. An apparatus, comprising:

a first group of memory cells coupled to a first access line and a plurality of sense lines configured to store a number of first elements;

a second group of memory cells coupled to a second access line and the plurality of sense lines configured to store a number of second elements; and

a third group of memory cells coupled to a plurality of access lines and to the plurality of sense lines; and

a controller configured to cause a plurality of corner turn operations on the number of first elements and the number of second elements to be performed using sensing circuitry;

wherein the plurality of corner turn operations comprises;

relocating a first data unit of each of the number of first and second elements from being stored in memory cells coupled to the first access line and the second access line, respectively, to being stored in memory cells of the third group of memory cells coupled to a third access line of the plurality of access lines.

23. The apparatus of claim 22, wherein the controller is further configured to operate the memory cells and the sensing circuitry to relocate a second data unit of each of the number of first and second elements from being stored in memory cells coupled to the first access line and the second access line, respectively, to being stored in memory cells of the third group of memory cells coupled to a fourth access line of the plurality of access lines.

24. The apparatus of claim 22, wherein the first access line, the second access line, and the plurality of access lines are different access lines.