Apparatuses and methods for shifting data

• US 9,659,610 B1
• Filed: 05/18/2016
• Issued: 05/23/2017
• Est. Priority Date: 05/18/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hush, Glen E.
• Primary Examiner(s): Le, Toan
• Application Number:
  US15/158,205
• Time in Patent Office: 370 Days
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence
• CPC Class Codes: G11C 7/1036 using data shift registers
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments include an apparatus comprising pre-charge lines and n-channel transistors without complementary p-channel transistors. A number of embodiments include a method comprising shifting data by pre-charging nodes with an operating voltage.

Claims

1. An apparatus, comprising:

a first pre-charge line;

a second pre-charge line;

a first p-channel transistor including a gate coupled to the first pre-charge line, and a first terminal coupled to a first sense line and a second terminal coupled to a first voltage supply node;

a first n-channel transistor including a gate coupled to a first control line and a terminal coupled to the first sense line;

a first inverter including an input coupled to the first sense line;

a second p-channel transistor including a gate coupled to the second pre-charge line, and a first terminal coupled to a second sense line and a second terminal coupled to a second voltage supply node;

a second n-channel transistor including a gate coupled to a second control line, a first terminal coupled to an output of the first inverter, and a second terminal coupled to the second sense line; and

a second inverter including an input coupled to the second sense line.

2. The apparatus of claim 1, wherein the apparatus is a shift register.

3. The apparatus of claim 1, wherein the first sense line is coupled to a first memory cell and is on pitch therewith;

and

wherein the second sense line is coupled to a second memory cell and is on pitch therewith.

4. The apparatus of claim 1, wherein the first p-channel transistor, the first n-channel transistor, the first inverter, the second p-channel transistor, the second n-channel transistor, and the second inverter collectively comprise a compute component,

wherein the compute component is on pitch with the first sense line and the second sense line;

and

wherein the apparatus includes a plurality of compute components.

5. The apparatus of claim 1, further comprising:

a third n-channel transistor including a gate coupled to a third control line, a first terminal coupled to the first sense line, and a second terminal coupled to an output of the second inverter; and

a fourth n-channel transistor including a gate coupled to a fourth control line and a terminal coupled to the second sense line.

6. The apparatus of claim 5, wherein the first p-channel transistor, the first n-channel transistor, the first inverter, the second p-channel transistor, the second n-channel transistor, the second inverter, the third n-channel transistor, and the fourth n-channel transistor collectively comprise a compute component,

wherein the compute component is on pitch with the first sense line and the second sense line;

and

wherein the apparatus includes a plurality of compute components.

7. An apparatus, comprising:

an array comprising a plurality of columns of memory cells; and

a controller coupled to the array and configured to;

shift data from a first compute component coupled to a first column of memory cells to a second compute component coupled to a second column of memory cells;

wherein, in order to shift the data, the controller is configured to;

pre-charge a first node of the first compute component with an operating voltage; and

pre-charge a second node of the first compute component with the operating voltage.

8. The apparatus of claim 7, wherein the apparatus further comprises:

a first pre-charge line; and

a second pre-charge line;

wherein the first compute component comprises;

a first transistor coupled to the first pre-charge line and the first node; and

a second transistor coupled to the second pre-charge line and the second node;

wherein, in order to shift the data, the controller is further configured to;

enable the first pre-charge line to pass the operating voltage to the first node; and

enable the second pre-charge line to pass the operating voltage to the second node.

9. The apparatus of claim 8, wherein, in order to shift the data, the controller is further configured to:

pre-charge the first node prior to enabling a first signal control line; and

pre-charge the second node prior to enabling a second signal control line.

10. The apparatus of claim 8, wherein the apparatus further comprises a third transistor coupled to the first node of the first compute component, a node of the second compute component, and a third signal control line;

wherein the first compute component and the second compute component are separated by at least one additional compute component; and

wherein the controller is further configured to pre-charge the first node of the first compute component prior to enabling the third signal control line.

11. The apparatus of claim 8, wherein the apparatus further comprises a third transistor coupled to the second node of the first compute component, a node of the second compute component, and a third signal control line;

wherein the first compute component and the second compute component are separated by at least one additional compute component; and

wherein the controller is further configured to pre-charge the first node of the first compute component prior to enabling the third signal control line.

12. The apparatus of claim 8, wherein the first compute component further comprises:

a third transistor coupled to the first node; and

a fourth transistor coupled to the second node;

wherein the third transistor and the fourth transistor are configured to pass a low voltage relative to the operating voltage.

13. The apparatus of claim 7, wherein the apparatus further comprises:

a first sense amplifier coupled to the first compute component and the first column of memory cells;

a first logical operation selection logic coupled to the first sense amplifier;

a second sense amplifier coupled to the second compute component and the second column of memory cells; and

a second logical operation selection logic coupled to the second sense amplifier.

14. The apparatus of claim 13, wherein the controller is further configured to cause logical operations to be performed, in parallel, using data values stored in the first column of memory cells and the second column of memory cells.

15. The apparatus of claim 14, wherein the controller is further configured to cause logical operations to be performed without transferring data via a bus.

16. A method for shifting data from a first compute component to a second compute component, comprising:

applying a first signal to a first pre-charge line that is coupled to a gate of a first p-channel transistor;

applying a second signal to a first control line that is coupled to a gate of a first n-channel transistor;

inverting a signal between the first n-channel transistor and a second n-channel transistor;

applying a third signal to a second pre-charge line that is coupled to gate of a second p-channel transistor;

applying a fourth signal to a second control line that is coupled to a gate of a second n-channel transistor; and

inverting a signal between the second n-channel transistor and a n-channel transistor of the second compute component.

17. The method of claim 16, wherein the method includes shifting the data from the first compute component to a third compute component by applying a fifth signal to a third control line that is coupled to a gate of a third n-channel transistor,

wherein the first compute component is separated from the third compute component by the second compute component.

18. The method of claim 16, wherein the method includes shifting the data from the second compute component to the first compute component by:

applying a fifth signal to a third control line that is coupled to a gate of a third n-channel transistor; and

applying a sixth signal to a fourth control line that is coupled to a gate of a fourth n-channel transistor.

19. The method of claim 18, wherein the method includes shifting the data from a third compute component to the first compute component by applying a seventh signal to a fifth control line that is coupled to a gate of a fifth n-channel transistor.

20. The method of claim 16, wherein shifting the data from the first compute component to the second compute component includes shifting a data value resulting from a logical operation.